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v5.1
SX-A Family FPGAs
Leading-Edge Performance
* * 250 MHz System Performance 350 MHz Internal Performance * * * * * * * * * *
TM
Specifications
* * * * 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops 0.22 / 0.25 CMOS Process Technology
Features
* * * * Hot-Swap Compliant I/Os Power-Up/Down Friendly (No Sequencing Required for Supply Voltages) 66 MHz PCI Compliant Nonvolatile, Single-Chip Solution
Configurable I/O Support for 3.3 V / 5 V PCI, 5 V TTL, 3.3 V LVTTL, 2.5 V LVCMOS2 2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with 5 V Input Tolerance and 5 V Drive Strength Devices Support Multiple Temperature Grades Configurable Weak-Resistor Pull-Up or Pull-Down for I/O at Power-Up Individual Output Slew Rate Control Up to 100% Resource Utilization and 100% Pin Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Boundary-Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Actel Secure Programming Technology with FuseLockTM Prevents Reverse Engineering and Design Theft
Table 1 * SX-A Product Profile Device Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks Boundary Scan Testing 3.3 V / 5 V PCI Input Set-Up (External) Speed Grades Temperature Grades Package (by pin count) PQFP TQFP PBGA FBGA CQFP A54SX08A 8,000 12,000 768 512 256 512* 130 3 0 Yes Yes 0 ns -F, Std, -1, -2 C, I, A, M 208 100, 144 - 144 - A54SX16A 16,000 24,000 1,452 924 528 990 180 3 0 Yes Yes 0 ns -F, Std, -1, -2, -3 C, I, A, M 208 100, 144 - 144, 256 - A54SX32A 32,000 48,000 2,880 1,800 1,080 1,980 249 3 0 Yes Yes 0 ns -F, Std, -1, -2, -3 C, I, A, M 208 100, 144, 176 329 144, 256, 484 208, 256 A54SX72A 72,000 108,000 6,036 4,024 2,012 4,024 360 3 4 Yes Yes 0 ns -F, Std, -1, -2, -3 C, I, A, M 208 - - 256, 484 208, 256
Note: *A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers
February 2005 (c) 2005 Actel Corporation
i See the Actel website for the latest version of the datasheet.
SX-A Family FPGAs
Ordering Information
A54SX16A 2 PQ 208
Application (Temperature Range) Blank = Commercial (0 to +70) I = Industrial (-40 to +85C) A = Automotive (-40 to +125C) M = Military (-55 to +125C) B = MIL-STD-883 Class B Package Lead Count Package Type BG = 1.27 mm Plastic Ball Grid Array FG = 1.0 mm Fine Pitch Ball Grid Array PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack CQ = Ceramic Quad Flat Pack* Speed Grade Blank = Standard Speed -1 = Approximately 15% Faster than Standard -2 = Approximately 25% Faster than Standard -3 = Approximately 35% Faster than Standard -F = Approximately 40% Slower than Standard Part Number A54SX08A = 12,000 System Gates A54SX16A = 24,000 System Gates A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates
Note: *For more information about the CQFP package options, refer to the HiRel SX-A datasheet.
Device Resources
User I/Os (Including Clock Buffers) Device A54SX08A A54SX16A A54SX32A A54SX72A 208-Pin PQFP 130 175 174 171 100-Pin TQFP 81 81 81 - 144-Pin TQFP 113 113 113 - 176-Pin TQFP - - 147 - 329-Pin PBGA - - 249 - 144-Pin FBGA 111 111 111 - 256-Pin FBGA - 180 203 203 484-Pin FBGA - - 249 360
Notes: Package Definitions: PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array
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SX-A Family FPGAs
Temperature Grade Offering
Package PQ208 TQ100 TQ144 TQ176 BG329 FG144 FG256 FG484 CQ208 CQ256 Notes: 1. 2. 3. 4. 5. 6. 7. C = Commercial I = Industrial A = Automotive M = Military B = Mil-Std-883 Class B For more information regarding automotive products, refer to the SX-A Automotive Family FPGAs datasheet. For more information regarding Mil-Temp and ceramic packages, refer to the HiRel SX-A Family FPGAs datasheet. C,I,A,M C,I,A,M C,I,A,M A54SX08A C,I,A,M C,I,A,M C,I,A,M A54SX16A C,I,A,M C,I,A,M C,I,A,M A54SX32A C,I,A,M C,I,A,M C,I,A,M C,I,M C,I,M C,I,A,M C,I,A,M C,I,M C,M,B C,M,B C,I,A,M C,I,A,M C,M,B C,M,B A54SX72A C,I,A,M
Speed Grade and Temperature Grade Matrix
F Commercial Industrial Automotive Military Mil-Std. 883B Notes: 1. For more information regarding automotive products, refer to the SX-A Automotive Family FPGAs datasheet. 2. For more information regarding Mil-Temp and ceramic packages, refer to the HiRel SX-A Family FPGAs datasheet. Std -1 -2 -3
Contact your Actel Sales representative for more information on availability.
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Table of Contents
General Description
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Detailed Specifications
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Typical SX-A Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 PCI Compliance for the SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Package Pin Assignments
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 329-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
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Table of Contents
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
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SX-A Family FPGAs
General Description
Introduction
The Actel SX-A family of FPGAs offers a cost-effective, single-chip solution for low-power, high-performance designs. Fabricated on 0.22 m / 0.25 m CMOS antifuse technology and with the support of 2.5 V, 3.3 V and 5 V I/Os, the SX-A is a versatile platform to integrate designs while significantly reducing timeto-market.
SX-A Family Architecture
The SX-A family's device architecture provides a unique approach to module organization and chip routing that satisfies performance requirements and delivers the most optimal register/logic mix for a wide variety of applications. Interconnection between these logic modules is achieved using Actel's patented metal-to-metal programmable antifuse interconnect elements (Figure 1-1). The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection.
Routing Tracks
Amorphous Silicon/ Dielectric Antifuse Metal 4 Tungsten Plug Via
Metal 3 Tungsten Plug Via
Metal 2
Metal 1 Tungsten Plug Contact
Silicon Substrate
Note: The A54SX72A device has four layers of metal with the antifuse between Metal 3 and Metal 4. The A54SX08A, A54SX16A, and A54SX32A devices have three layers of metal with the antifuse between Metal 2 and Metal 3. Figure 1-1 * SX-A Family Interconnect Elements
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SX-A Family FPGAs
Logic Module Design
The SX-A family architecture is described as a "sea-ofmodules" architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. The Actel SX-A family provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable, using the S0 and S1 lines control signals (Figure 1-2). The R-cell registers feature programmable clock polarity selectable on a register-byregister basis. This provides additional flexibility while allowing mapping of synthesized functions into the SX-A FPGA. The clock source for the R-cell can be chosen from either the hardwired clock, the routed clocks, or internal logic. The C-cell implements a range of combinatorial functions of up to five inputs (Figure 1-3). Inclusion of the DB input and its associated inverter function allows up to 4,000
different combinatorial functions to be implemented in a single module. An example of the flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions with 1.9 ns propagation delays.
Module Organization
All C-cell and R-cell logic modules are arranged into horizontal banks called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. Clusters are grouped together into SuperClusters (Figure 1-4 on page 1-3). SuperCluster 1 is a two-wide grouping of Type 1 Clusters. SuperCluster 2 is a two-wide group containing one Type 1 Cluster and one Type 2 Cluster. SX-A devices feature more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops.
S0
Routed Data Input S1 PRE
DirectConnect Input
DQ
Y
HCLK CLKA, CLKB, Internal Logic
Figure 1-2 * R-Cell
CLR CKS CKP
D0 D1 Y D2 D3 Sa Sb
DB A0 B0
Figure 1-3 * C-Cell
A1 B1
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SX-A Family FPGAs
Routing Resources
The routing and interconnect resources of SX-A devices are in the top two metal layers above the logic modules (Figure 1-1 on page 1-1), providing optimal use of silicon, thus enabling the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using the Actel patented metal-to-metal programmable antifuse interconnect elements. The antifuses are normally open circuits and, when programmed, form a permanent low-impedance connection. Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 1-5 on page 1-4 and Figure 1-6 on page 1-4). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance, which is often required in applications such as fast counters, state machines, and data path logic. The interconnect elements (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-Cell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable
R-Cell
Routed S1 S0 Data Input PRE DirectConnect Input D Q Y D2 D3 Sa HCLK CLKA, CLKB, Internal Logic Sb D0 D1 Y
interconnection to achieve its fast signal propagation time of less than 0.1 ns. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster, and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum pin-to-pin propagation time of 0.3 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. The Actel segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100% automatic place-and-route software to minimize signal propagation delays. The general system of routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, most connections typically require three or fewer antifuses, resulting in fast and predictable performance. The unique local and general routing structure featured in SX-A devices allows 100% pin-locking with full logic utilization, enables concurrent printed circuit board (PCB) development, reduces design time, and allows designers to achieve performance goals with minimum effort.
C-Cell
CLR DB CKS CKP A0 B0 A1 B1
Cluster 1
Cluster 1
Cluster 2
Cluster 1
Type 1 SuperCluster
Figure 1-4 * Cluster Organization
Type 2 SuperCluster
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SX-A Family FPGAs
DirectConnect * No Antifuses * 0.1 ns Maximum Routing Delay FastConnect * One Antifuse * 0.3 ns Maximum Routing Delay Routing Segments * Typically Two Antifuses * Max. Five Antifuses
Figure 1-5 * DirectConnect and FastConnect for Type 1 SuperClusters
DirectConnect * No antifuses for smallest routing delay FastConnect * One antifuse
Routing Segments * Typically 2 antifuses * Max. 5 antifuses
Figure 1-6 * DirectConnect and FastConnect for Type 2 SuperClusters
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SX-A Family FPGAs
Clock Resources
Actel's high-drive routing structure provides three clock networks (Table 1-1). The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select multiplexor (MUX) in each R-cell. HCLK cannot be connected to combinatorial logic. This provides a fast propagation path for the clock signal. If not used, this pin must be set as Low or High on the board. It must not be left floating. Figure 1-7 describes the clock circuit used for the constant load HCLK and the macros supported. HCLK does not function until the fourth clock cycle each time the device is powered up to prevent false output levels due to any possible slow power-on-reset signal and fast start-up clock circuit. To activate HCLK from the first cycle, the TRST pin must be reserved in the Design software and the pin must be tied to GND on the board. Two additional clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the SX-A device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB pins are not used or sourced from signals, these pins must be set as Low or High on the board. They must not be left floating. Figure 1-8 describes the CLKA
Table 1-1 * SX-A Clock Resources A54SX08A Routed Clocks (CLKA, CLKB) Hardwired Clocks (HCLK) Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD) 2 1 0 A54SX16A 2 1 0 A54SX32A 2 1 0 A54SX72A 2 1 4
and CLKB circuit used and the macros supported in SX-A devices with the exception of A54SX72A. In addition, the A54SX72A device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD-- corresponding to bottom-left, bottom-right, top-left, and top-right locations on the die, respectively), which can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to an entire quadrant of the chip, or they can be grouped together to drive multiple quadrants (Figure 1-9 on page 1-6). QCLK pins can function as user I/O pins. If not used, the QCLK pins must be tied Low or High on the board and must not be left floating. For more information on how to use quadrant clocks in the A54SX72A device, refer to the Global Clock Networks in Actel's Antifuse Devices and Using A54SX72A and RT54SX72S Quadrant Clocks application notes. The CLKA, CLKB, and QCLK circuits for A54SX72A as well as the macros supported are shown in Figure 1-10 on page 1-6. Note that bidirectional clock buffers are only available in A54SX72A. For more information, refer to the "Pin Description" section on page 1-14.
Constant Load Clock Network HCLKBUF
Figure 1-7 * SX-A HCLK Clock Buffer
Clock Network
From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI
Figure 1-8 * SX-A Routed Clock Buffer
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SX-A Family FPGAs
4 QCLKBUFS
Quadrant 2
4 5:1 5:1
Quadrant 3
QCLKINT (to array) 4 Quadrant 0 5:1
QCLKINT (to array)
5:1
Quadrant 1
QCLKINT (to array)
Figure 1-9 * SX-A QCLK Architecture
QCLKINT (to array)
OE From Internal Logic
Clock Network
From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI CLKBIBUF CLKBIBUFI
Figure 1-10 * A54SX72A Routed Clock and QCLK Buffer
QCLKBUF QCLKBUFI QCLKINT QCLKINTI QCLKBIBUF QCLKBIBUFI
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Other Architectural Features
Technology
The Actel SX-A family is implemented on a high-voltage, twin-well CMOS process using 0.22 / 0.25 design rules. The metal-to-metal antifuse is comprised of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ('on' state) resistance of 25 with capacitance of 1.0 fF for low signal impedance.
I/O Modules
For a simplified I/O schematic, refer to Figure 1 in the application note, Actel eX, SX-A, and RTSX-S I/Os. Each user I/O on an SX-A device can be configured as an input, an output, a tristate output, or a bidirectional pin. Mixed I/O standards can be set for individual pins, though this is only allowed with the same voltage as the input. These I/Os, combined with array registers, can achieve clock-to-output-pad timing as fast as 3.8 ns, even without the dedicated I/O registers. In most FPGAs, I/O cells that have embedded latches and flip-flops, requiring instantiation in HDL code; this is a design complication not encountered in SX-A FPGAs. Fast pinto-pin timing ensures that the device is able to interface with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. All unused I/Os are configured as tristate outputs by the Actel Designer software, for maximum flexibility when designing new boards or migrating existing designs. SX-A I/Os should be driven by high-speed push-pull devices with a low-resistance pull-up device when being configured as tristate output buffers. If the I/O is driven by a voltage level greater than VCCI and a fast push-pull device is NOT used, the high-resistance pull-up of the driver and the internal circuitry of the SX-A I/O may create a voltage divider. This voltage divider could pull the input voltage below specification for some devices connected to the driver. A logic '1' may not be correctly presented in this case. For example, if an open drain driver is used with a pull-up resistor to 5 V to provide the logic '1' input, and VCCI is set to 3.3 V on the SX-A device, the input signal may be pulled down by the SX-A input. Each I/O module has an available power-up resistor of approximately 50 k that can configure the I/O in a known state during power-up. For nominal pull-up and pull-down resistor values, refer to Table 1-4 on page 1-8 of the application note Actel eX, SX-A, and RTSX-S I/Os. Just slightly before VCCA reaches 2.5 V, the resistors are disabled, so the I/Os will be controlled by user logic. See Table 1-2 on page 1-8 and Table 1-3 on page 1-8 for more information concerning available I/O features.
Performance
The unique architectural features of the SX-A family enable the devices to operate with internal clock frequencies of 350 MHz, causing very fast execution of even complex logic functions. The SX-A family is an optimal platform upon which to integrate the functionality previously contained in multiple complex programmable logic devices (CPLDs). In addition, designs that previously would have required a gate array to meet performance goals can be integrated into an SX-A device with dramatic improvements in cost and time-to-market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance.
User Security
Reverse engineering is virtually impossible in SX-A devices because it is extremely difficult to distinguish between programmed and unprogrammed antifuses. In addition, since SX-A is a nonvolatile, single-chip solution, there is no configuration bitstream to intercept at device power-up. The Actel FuseLock advantage ensures that unauthorized users will not be able to read back the contents of an Actel antifuse FPGA. In addition to the inherent strengths of the architecture, special security fuses that prevent internal probing and overwriting are hidden throughout the fabric of the device. They are located where they cannot be accessed or bypassed without destroying access to the rest of the device, making both invasive and more-subtle noninvasive attacks ineffective against Actel antifuse FPGAs. Look for this symbol to ensure your valuable IP is secure (Figure 1-11).
ue
Figure 1-11 * FuseLock
For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note.
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SX-A Family FPGAs
Power-Up/Down and Hot Swapping
SX-A I/Os are configured to be hot-swappable, with the exception of 3.3 V PCI. During power-up/down (or partial up/down), all I/Os are tristated. VCCA and VCCI do not have to be stable during power-up/down, and can be powered up/down in any order. When the SX-A device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device's output pins are driven to a high impedance state until normal chip operating conditions
Table 1-2 * I/O Features Function Input Buffer Threshold Selections Description * * * * * * 5 V: PCI, TTL 3.3 V: PCI, LVTTL 2.5 V: LVCMOS2 (commercial only) 5 V: PCI, TTL 3.3 V: PCI, LVTTL 2.5 V: LVCMOS2 (commercial only)
are reached. Table 1-4 summarizes the VCCA voltage at which the I/Os behave according to the user's design for an SX-A device at room temperature for various ramp-up rates. The data reported assumes a linear ramp-up profile to 2.5 V. For more information on power-up and hot-swapping, refer to the application note, Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications.
Flexible Output Driver
Output Buffer
"Hot-Swap" Capability (3.3 V PCI is not hot swappable) * I/O on an unpowered device does not sink current * Can be used for "cold-sparing" Selectable on an individual I/O basis Individually selectable slew rate; high slew or low slew (The default is high slew rate). The slew is only affected on the falling edge of an output. Rising edges of outputs are not affected. Individually selectable pull-ups and pull-downs during power-up (default is to power-up in tristate) Enables deterministic power-up of device VCCA and VCCI can be powered in any order
Power-Up
Table 1-3 * I/O Characteristics for All I/O Configurations Hot Swappable TTL, LVTTL, LVCMOS2 3.3 V PCI 5 V PCI Yes No Yes Slew Rate Control Yes. Only affects falling edges of outputs No. High slew rate only No. High slew rate only Power-Up Resistor Pull-up or pull-down Pull-up or pull-down Pull-up or pull-down
Table 1-4 * Power-Up Time at which I/Os Become Active Supply Ramp Rate Units A54SX08A A54SX16A A54SX32A A54SX72A 0.25 V/s s 10 10 10 10 0.025 V/s s 96 100 100 100 5 V/ms ms 0.34 0.36 0.46 0.41 2.5 V/ms ms 0.65 0.62 0.74 0.67 0.5 V/ms ms 2.7 2.5 2.8 2.6 0.25 V/ms ms 5.4 4.7 5.2 5.0 0.1 V/ms ms 12.9 11.0 12.1 12.1 0.025 V/ms ms 50.8 41.6 47.2 47.2
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Boundary-Scan Testing (BST)
All SX-A devices are IEEE 1149.1 compliant and offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. The BST function is controlled through the special JTAG pins (TMS, TDI, TCK, TDO, and TRST). The functionality of the JTAG pins is defined by two available modes: Dedicated and Flexible. TMS cannot be employed as a user I/O in either mode.
Flexible Mode
In Flexible mode, TDI, TCK, and TDO may be employed as either user I/Os or as JTAG input pins. The internal resistors on the TMS and TDI pins are not present in flexible JTAG mode. To select the Flexible mode, uncheck the Reserve JTAG box in the Device Selection Wizard dialog in the Actel Designer software. In Flexible mode, TDI, TCK, and TDO pins may function as user I/Os or BST pins. The functionality is controlled by the BST Test Access Port (TAP) controller. The TAP controller receives two control inputs, TMS and TCK. Upon power-up, the TAP controller enters the Test-Logic-Reset state. In this state, TDI, TCK, and TDO function as user I/Os. The TDI, TCK, and TDO are transformed from user I/Os into BST pins when a rising edge on TCK is detected while TMS is at logic low. To return to Test-Logic Reset state, TMS must be high for at least five TCK cycles. An external 10 k pull-up resistor to VCCI should be placed on the TMS pin to pull it High by default. Table 1-6 describes the different configuration requirements of BST pins and their functionality in different modes.
Table 1-6 * Boundary-Scan Pin Configurations and Functions Designer "Reserve JTAG" Selection Checked Unchecked Unchecked TAP Controller State Any Test-Logic-Reset Any EXCEPT TestLogic-Reset
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST; designers cannot use them as regular I/Os. An internal pull-up resistor is automatically enabled on both TMS and TDI pins, and the TMS pin will function as defined in the IEEE 1149.1 (JTAG) specification. To select Dedicated mode, the user must reserve the JTAG pins in Actel's Designer software. Reserve the JTAG pins by checking the Reserve JTAG box in the Device Selection Wizard (Figure 1-12). The default for the software is Flexible mode; all boxes are unchecked. Table 1-5 lists the definitions of the options in the Device Selection Wizard.
Mode Dedicated (JTAG) Flexible (User I/O) Flexible (JTAG)
Figure 1-12 * Device Selection Wizard Table 1-5 * Reserve Pin Definitions Pin Reserve JTAG Function Keeps pins from being used and changes the behavior of JTAG pins (no pull-up on TMS) Test Regular I/O or JTAG reset with an internal pull-up Keeps pins from being used or regular I/O
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan Reset pin when the Reserve JTAG Test Reset option is selected as shown in Figure 1-12. An internal pull-up resistor is permanently enabled on the TRST pin in this mode. Actel recommends connecting this pin to ground in normal operation to keep the JTAG state controller in the Test-Logic-Reset state. When JTAG is being used, it can be left floating or can be driven high. When the Reserve JTAG Test Reset option is not selected, this pin will function as a regular I/O. If unused as an I/O in the design, it will be configured as a tristated output.
Reserve Reset
JTAG
Reserve Probe
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SX-A Family FPGAs
JTAG Instructions
Table 1-7 lists the supported instructions with the corresponding IR codes for SX-A devices. Table 1-8 lists the codes returned after executing the IDCODE instruction for SX-A devices. Note that bit 0 is always '1'. Bits 11-1 are always '02F', which is the Actel manufacturer code.
Table 1-7 * JTAG Instruction Code Instructions (IR4:IR0) EXTEST SAMPLE/PRELOAD INTEST USERCODE IDCODE HighZ CLAMP Diagnostic BYPASS Reserved Table 1-8 * JTAG Instruction Code Device A54SX08A A54SX16A Process 0.22 0.22 0.25 A54SX32A 0.2 2 0.25 A54SX72A 0.22 0.25 Revision 0 1 0 1 1 0 1 1 0 1 1 Bits 31-28 8, 9 A, B 9 B B 9 B B 9 B B Bits 27-12 40B4, 42B4 40B4, 42B4 40B8, 42B8 40B8, 42B8 22B8 40BD, 42BD 40BD, 42BD 22BD 40B2, 42B2 40B2, 42B2 22B2 Binary Code 00000 00001 00010 00011 00100 01110 01111 10000 11111 All others
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SX-A Family FPGAs
Probing Capabilities
SX-A devices also provide an internal probing capability that is accessed with the JTAG pins. The Silicon Explorer II diagnostic hardware is used to control the TDI, TCK, TMS, and TDO pins to select the desired nets for debugging. The user assigns the selected internal nets in Actel Silicon Explorer II software to the PRA/PRB output pins for observation. Silicon Explorer II automatically places the device into JTAG mode. However, probing functionality is only activated when the TRST pin is driven high or left floating, allowing the internal pull-up resistor to pull TRST High. If the TRST pin is held Low, the TAP controller remains in the Test-Logic-Reset state so no probing can be performed. However, the user must drive the TRST pin High or allow the internal pull-up resistor to pull TRST High.
TRST1 Low High Flexible Low High
When selecting the Reserve Probe Pin box as shown in Figure 1-12 on page 1-9, direct the layout tool to reserve the PRA and PRB pins as dedicated outputs for probing. This Reserve option is merely a guideline. If the designer assigns user I/Os to the PRA and PRB pins and selects the Reserve Probe Pin option, Designer Layout will override the Reserve Probe Pin option and place the user I/Os on those pins. To allow probing capabilities, the security fuse must not be programmed. Programming the security fuse disables the JTAG and probe circuitry. Table 1-9 summarizes the possible device configurations for probing once the device leaves the Test-Logic-Reset JTAG state.
Table 1-9 * Device Configuration Options for Probe Capability (TRST Pin Reserved) JTAG Mode Dedicated Security Fuse Programmed No No No No Yes Notes: 1. If the TRST pin is not reserved, the device behaves according to TRST = High as described in the table. 2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input signals will not pass through these pins and may cause contention. 3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by the Designer software. PRA, PRB2 User I/O3 Probe Circuit Outputs User I/O3 TDI, TCK, TDO2 JTAG Disabled JTAG I/O User I/O3 JTAG I/O Probe Circuit Secured
Probe Circuit Outputs Probe Circuit Secured
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SX-A Family FPGAs
SX-A Probe Circuit Control Pins
SX-A devices contain internal probing circuitry that provides built-in access to every node in a design, enabling 100% real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy to use, integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. The Silicon Explorer II tool uses the boundary-scan ports (TDI, TCK, TMS, and TDO) to select the desired nets for verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 1-13 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification.
Design Considerations
In order to preserve device probing capabilities, users should avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, critical input signals through these pins are not available. In addition, the security fuse must not be programmed to preserve probing capabilities. Actel recommends that you use a 70 series termination resistor on every probe connector (TDI, TCK, TMS, TDO, PRA, PRB). The 70 series termination is used to prevent data transmission corruption during probing and reading back the checksum.
Additional Channels
16
TDI TCK Serial Connection Silicon Explorer II TMS 70 70
70 70 70 TDO PRA
SX-A FPGA
70
Figure 1-13 * Probe Setup
PRB
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SX-A Family FPGAs
Design Environment
The SX-A family of FPGAs is fully supported by both Actel Libero(R) Integrated Design Environment (IDE) and Designer FPGA development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify(R) for Actel from Synplicity(R), ViewDraw(R) for Actel from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM from SynaptiCADTM, and Designer software from Actel. Refer to the Libero IDE flow diagram for more information (located on the Actel website). Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel's integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation in your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.
Related Documents
Application Notes
Global Clock Networks in Actel's Antifuse Devices http://www.actel.com/documents/GlobalClk.pdf Using A54SX72A and RT54SX72S Quadrant Clocks http://www.actel.com/documents/QCLK.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/ AntifuseSecurityAN.pdf Actel eX, SX-A, and RTSX-S I/Os http://www.actel.com/documents/antifuseIOan.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and ColdSparing Applications http://www.actel.com/documents/ HotSwapColdSparing.pdf
Datasheets
HiRel SX-A Family FPGAs http://www.actel.com/documents/HRSXADS.pdf SX-A Automotive Family FPGAs http://www.actel.com/documents/SXAAutoDS.pdf
Programming
Programming support is provided through Actel's Silicon Sculptor II, a single-site programmer driven via a PC based GUI. In addition, BP Microsystems offers multi-site programmers that provide qualified support for Actel devices. Factory programming is available for high volume production needs. For detail information on programming, visit: http://www.actel.com/products/tools/prog.aspx .
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SX-A Family FPGAs
Pin Description
CLKA/B, I/O Clock A and B
PRA/B, I/O
Probe A/B
These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. The clock input is buffered prior to clocking the R-cells. When not used, this pin must be tied Low or High (NOT left floating) on the board to avoid unwanted power consumption. For A54SX72A, these pins can also be configured as user I/Os. When employed as user I/Os, these pins offer builtin programmable pull-up or pull-down resistors active during power-up only. When not used, these pins must be tied Low or High (NOT left floating).
QCLKA/B/C/D, I/O Quadrant Clock A, B, C, and D
The Probe pin is used to output data from any userdefined design node within the device. This independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality.
TCK, I/O Test Clock
These four pins are the quadrant clock inputs and are only used for A54SX72A with A, B, C, and D corresponding to bottom-left, bottom-right, top-left, and top-right quadrants, respectively. They are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. Each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. The clock input is buffered prior to clocking the R-cells. When not used, these pins must be tied Low or High on the board (NOT left floating). These pins can also be configured as user I/Os. When employed as user I/Os, these pins offer built-in programmable pull-up or pull-down resistors active during power-up only.
GND HCLK Ground Dedicated (Hardwired) Array Clock
Test clock input for diagnostic probe and device programming. In Flexible mode, TCK becomes active when the TMS pin is set Low (refer to Table 1-6 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDI, I/O Test Data Input
Serial input for boundary scan testing and diagnostic probe. In Flexible mode, TDI is active when the TMS pin is set Low (refer to Table 1-6 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDO, I/O Test Data Output
Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set Low (refer to Table 1-6 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. When Silicon Explorer II is being used, TDO will act as an output when the checksum command is run. It will return to user /IO when checksum is complete.
TMS Test Mode Select
Low supply voltage.
This pin is the clock input for sequential modules. Input levels are compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. When not used, HCLK must be tied Low or High on the board (NOT left floating). When used, this pin should be held Low or High during power-up to avoid unwanted static power consumption.
I/O Input/Output
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible mode when the TMS pin is set Low, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 1-6 on page 1-9). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the logic reset state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The logic reset state is reached five TCK cycles after the TMS pin is set High. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications.
TRST, I/O Boundary Scan Reset Pin
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V PCI or 5 V PCI specifications. Unused I/O pins are automatically tristated by the Designer software.
NC No Connection
Once it is configured as the JTAG Reset pin, the TRST pin functions as an active low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal pull-up resistor. This pin functions as an I/O when the Reserve JTAG Reset Pin is not selected in Designer.
VCCI Supply Voltage
This pin is not connected to circuitry within the device and can be driven to any voltage or be left floating with no effect on the operation of the device.
Supply voltage for I/Os. See Table 2-2 on page 2-1. All VCCI power pins in the device should be connected.
VCCA Supply Voltage
Supply voltage for array. See Table 2-2 on page 2-1. All VCCA power pins in the device should be connected.
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SX-A Family FPGAs
Detailed Specifications
Operating Conditions
Table 2-1 * Absolute Maximum Ratings Symbol VCCI VCCA VI VO TSTG Parameter DC Supply Voltage for I/Os DC Supply Voltage for Arrays Input Voltage Output Voltage Storage Temperature Limits -0.3 to +6.0 -0.3 to +3.0 -0.5 to +5.75 -0.5 to +VCCI+0.5 -65 to +150 Units V V V V C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the "Recommended Operating Conditions". Table 2-2 * Recommended Operating Conditions Parameter Temperature Range 2.5 V Power Supply Range (VCCA and VCCI) 3.3 V Power Supply Range (VCCI) 5 V Power Supply Range (VCCI) Commercial 0 to +70 2.25 to 2.75 3.0 to 3.6 4.75 to 5.25 Industrial -40 to +85 2.25 to 2.75 3.0 to 3.6 4.75 to 5.25 Units C V V V
Typical SX-A Standby Current
Table 2-3 * Typical Standby Current for SX-A at 25C with VCCA = 2.5 V Product A54SX08A A54SX16A A54SX32A A54SX72A Table 2-4 * Supply Voltages VCCA 2. 5 V 2.5 V 2.5 V VCCI* 2.5 V 3.3 V 5V Maximum Input Tolerance 5.75 V 5.75 V 5.75 V Maximum Output Drive 2.7 V 3.6 V 5.25 V VCCI = 2.5 V 0.8 mA 0.8 mA 0.9 mA 3.6 mA VCCI = 3.3 V 1.0 mA 1.0 mA 1.0 mA 3.8 mA VCCI = 5 V 2.9 mA 2.9 mA 3.0 mA 4.5 mA
Note: *3.3 V PCI is not 5 V tolerant due to the clamp diode, but instead is 3.3 V tolerant.
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SX-A Family FPGAs
Electrical Specifications
Table 2-5 * 3.3 V LVTTL and 5 V TTL Electrical Specifications Commercial Symbol VOH VCCI = Minimum VI = VIH or VIL VCCI = Minimum VI = VIH or VIL VOL VCCI = Minimum VI = VIH or VIL VCCI = Minimum VI = VIH or VIL VIL VIH IIL/IIH IOZ tR , tF CIO ICC Input Low Voltage Input High Voltage Input Leakage Current, VIN = VCCI or GND Tristate Output Leakage Current Input Transition Time tR, tF I/O Capacitance Standby Current 2.0 -10 -10 Parameter (IOH = -1 mA) (IOH = -8 mA) (IOL= 1 mA) (IOL= 12 mA) Min. 0.9 VCCI 2.4 0.4 0.4 0.8 5.75 10 10 10 10 10 2.0 -10 -10 Max. Industrial Min. 0.9 VCCI 2.4 0.4 0.4 0.8 5.75 10 10 10 10 20 Max. Units V V V V V V A A ns pF mA
IV Curve* Can be derived from the IBIS model on the web. Note: *The IBIS model can be found at http://www.actel.com/techdocs/models/ibis.html. Table 2-6 * 2.5 V LVCMOS2 Electrical Specifications Commercial Symbol VOH VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VOL VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VDD = MIN, VI = VIH or VIL VIL VIH IIL/IIH IOZ tR , tF CIO ICC Input Low Voltage, VOUT VVOL(max) Input High Voltage, VOUT VVOH(min) Input Leakage Current, VIN = VCCI or GND Tristate Output Leakage Current, VOUT = VCCI or GND Input Transition Time tR, tF I/O Capacitance Standby Current Parameter (IOH = -100 A) (IOH = -1 mA) (IOH =--2 mA) (IOL= 100 A) (IOL= 1 mA) (IOL= 2 mA) -0.3 1.7 -10 -10 Min. 2.1 2.0 1.7 0.2 0.4 0.7 0.7 5.75 10 10 10 10 10 -0.3 1.7 -10 -10 Max. Industrial Min. 2.1 2.0 1.7 0.2 0.4 0.7 0.7 5.75 10 10 10 10 20 Max. Units V V V V V V V V A A ns pF mA
IV Curve* Can be derived from the IBIS model on the web. Note: *The IBIS model can be found at http://www.actel.com/techdocs/models/ibis.html.
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SX-A Family FPGAs
PCI Compliance for the SX-A Family
The SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
Table 2-7 * DC Specifications (5 V PCI Operation) Symbol VCCA VCCI VIH VIL IIH IIL VOH VOL CIN CCLK Notes: 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter includes FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Parameter Supply Voltage for Array Supply Voltage for I/Os Input High Voltage Input Low Voltage Input High Leakage Current1 Input Low Leakage Current Output High Voltage Output Low Voltage2
1
Condition
Min. 2.25 4.75 2.0 -0.5
Max. 2.75 5.25 5.75 0.8 70 -70 - 0.55 10 12
Units V V V V A A V V pF pF
VIN = 2.7 VIN = 0.5 IOUT = -2 mA IOUT = 3 mA, 6 mA
- - 2.4 - - 5
Input Pin Capacitance3 CLK Pin Capacitance
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SX-A Family FPGAs
Table 2-8 * AC Specifications (5 V PCI Operation) Symbol IOH(AC) Parameter Switching Current High Condition 0 < VOUT 1.4
1
Min. -44 (-44 + (VOUT - 1.4)/0.024) - - 95
Max. - - EQ 2-1 on page 2-5 -142 - - EQ 2-2 on page 2-5 206 - 5 5
Units mA mA - mA mA mA - mA mA V/ns V/ns
1.4 VOUT < 2.4 1, 2 3.1 < VOUT < VCCI (Test Point) IOL(AC) Switching Current Low VOUT = 3.1 3 VOUT 2.2
1 1 1, 3
2.2 > VOUT > 0.55
(VOUT/0.023) - - -25 + (VIN + 1)/0.015
0.71 > VOUT > 0 1, 3 (Test Point) ICL slewR slewF Notes: Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.71 3 -5 < VIN -1 0.4 V to 2.4 V load 2.4 V to 0.4 V load
4 4
1 1
1. Refer to the V/I curves in Figure 2-1 on page 2-5. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective diagrams in Figure 2-1 on page 2-5. The equation defined maximum should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
Pin Output Buffer 50 pF 1/2 in. max.
2 -4
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SX-A Family FPGAs
Figure 2-1 shows the 5 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.
200.0 IOL MAX Spec 150.0 100.0 IOL MIN Spec Current (mA) 50.0 0.0 0 -50.0 -100.0 -150.0 -200.0 IOH Voltage Out (V)
Figure 2-1 * 5 V PCI V/I Curve for SX-A Family
IOL
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
IOH MIN Spec
IOH MAX Spec
IOH = 11.9 * (VOUT - 5.25) * (VOUT + 2.45) for VCCI > VOUT > 3.1V
EQ 2-1
IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V
EQ 2-2
Table 2-9 * DC Specifications (3.3 V PCI Operation) Symbol VCCA VCCI VIH VIL IIPU IIL VOH VOL CIN CCLK Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Designers should ensure that the input buffer is conducting minimum current at this input voltage in applications sensitive to static power utilization. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Parameter Supply Voltage for Array Supply Voltage for I/Os Input High Voltage Input Low Voltage Input Pull-up Voltage1 Input Leakage Current2 Output High Voltage Output Low Voltage Input Pin Capacitance3 CLK Pin Capacitance 0 < VIN < VCCI IOUT = -500 A IOUT = 1,500 A - 5 Condition Min. 2.25 3.0 0.5VCCI -0.5 0.7VCCI -10 0.9VCCI Max. 2.75 3.6 VCCI + 0.5 0.3VCCI - +10 - 0.1VCCI 10 12 Units V V V V V A V V pF pF
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SX-A Family FPGAs
Table 2-10 * AC Specifications (3.3 V PCI Operation) Symbol IOH(AC) Parameter Switching Current High Condition 0 < VOUT 0.3VCCI
1
Min. -12VCCI (-17.1(VCCI - VOUT)) - -
1 1 1, 2
Max. - - EQ 2-3 on page 2-7 -32VCCI - - EQ 2-4 on page 2-7 38VCCI - - 4 4
Units mA mA - mA mA mA - mA mA mA V/ns V/ns
0.3VCCI VOUT < 0.9VCCI 1 0.7VCCI < VOUT < VCCI (Test Point) IOL(AC) Switching Current Low VOUT = 0.7VCC 2 VCCI > VOUT 0.6VCCI
16VCCI (26.7VOUT) - - -25 + (VIN + 1)/0.015 25 + (VIN - VCCI - 1)/0.015 1 1
0.6VCCI > VOUT > 0.1VCCI 0.18VCCI > VOUT > 0 1, 2 (Test Point) ICL ICH slewR slewF Notes: Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.18VCC 2 -3 < VIN -1 VCCI + 4 > VIN VCCI + 1 0.2VCCI - 0.6VCCI load
3
0.6VCCI - 0.2VCCI load 3
1. Refer to the V/I curves in Figure 2-2 on page 2-7. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D) are provided with the respective diagrams in Figure 2-2 on page 2-7. The equation defined maximum should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
Pin Output Buffer 10 pF 1 k/25
1/2 in. max.
Pin Output Buffer
1 k/25 10 pF
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v5.1
SX-A Family FPGAs
Figure 2-2 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.
150.0 IOL MAX Spec 100.0 50.0 0.0 0 -50.0 -100.0 -150.0 Voltage Out (V)
Figure 2-2 * 3.3 V PCI V/I Curve for SX-A Family
IOL
Current (mA)
IOL MIN Spec 0.5 IOH MIN Spec IOH IOH MAX Spec 1 1.5 2 2.5 3 3.5 4
IOH = (98.0/VCCI) * (VOUT - VCCI) * (VOUT + 0.4VCCI) for 0.7 VCCI < VOUT < VCCI
EQ 2-3
IOL = (256/VCCI) * VOUT * (VCCI - VOUT) for 0V < VOUT < 0.18 VCCI
EQ 2-4
v5.1
2-7
SX-A Family FPGAs
Power Dissipation
A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package used, the operating temperature, the operating current, and the system's ability to dissipate heat. A complete power evaluation should be performed early in the design process to help identify potential heat-related problems in the system and to prevent the system from exceeding the device's maximum allowed junction temperature. The actual power dissipated by most applications is significantly lower than the power the package can dissipate. However, a thermal analysis should be performed for all projects. To perform a power evaluation, follow these steps: 1. Estimate the power consumption of the application. 2. Calculate the maximum power allowed for the device and package. 3. Compare the estimated power and maximum power values.
Estimating Power Dissipation
The total power dissipation for the SX-A family is the sum of the DC power dissipation and the AC power dissipation: PTotal = PDC + PAC
EQ 2-5
DC Power Dissipation
The power due to standby current is typically a small component of the overall power. An estimation of DC power dissipation under typical conditions is given by: PDC = IStandby * VCCA
EQ 2-6
Note: For other combinations of temperature and voltage settings, refer to the eX, SX-A and RT54SX-S Power Calculator.
AC Power Dissipation
The power dissipation of the SX-A family is usually dominated by the dynamic power dissipation. Dynamic power dissipation is a function of frequency, equivalent capacitance, and power supply voltage. The AC power dissipation is defined as follows:
PAC = PC-cells + PR-cells + PCLKA + PCLKB + PHCLK + POutput Buffer + PInput Buffer EQ 2-7
or:
PAC =
VCCA2 * [(m * CEQCM * fm)C-cells + (m * CEQSM * fm)R-cells + (n * CEQI * fn)Input Buffer + (p * (CEQO + CL) * fp)Output Buffer + (0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))CLKA + (0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))CLKB + (0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK]
EQ 2-8
2 -8
v5.1
SX-A Family FPGAs
Where:
CEQCM = Equivalent capacitance of combinatorial modules (C-cells) in pF CEQSM = Equivalent capacitance of sequential modules (R-Cells) in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of CLKA/B in pF CEQHV = Variable capacitance of HCLK in pF CEQHF = Fixed capacitance of HCLK in pF CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average CLKA rate in MHz fq2 = Average CLKB rate in MHz fs1 = Average HCLK rate in MHz m = Number of logic modules switching at fm n = Number of input buffers switching at fn p = Number of output buffers switching at fp q1 = Number of clock loads on CLKA q2 = Number of clock loads on CLKB r1 = Fixed capacitance due to CLKA r2 = Fixed capacitance due to CLKB s1 = Number of clock loads on HCLK x = Number of I/Os at logic low y = Number of I/Os at logic high Table 2-11 * CEQ Values for SX-A Devices A54SX08A Combinatorial modules (CEQCM) Sequential modules (CEQCM) Input buffers (CEQI) Output buffers (CEQO) Routed array clocks (CEQCR) Dedicated array clocks - variable (CEQHV) Dedicated array clocks - fixed (CEQHF) Routed array clock A (r1) 1.70 pF 1.50 pF 1.30 pF 7.40 pF 1.05 pF 0.85 pF 30.00 pF 35.00 pF A54SX16A 2.00 pF 1.50 pF 1.30 pF 7.40 pF 1.05 pF 0.85 pF 55.00 pF 50.00 pF A54SX32A 2.00 pF 1.30 pF 1.30 pF 7.40 pF 1.05 pF 0.85 pF 110.00 pF 90.00 pF A54SX72A 1.80 pF 1.50 pF 1.30 pF 7.40 pF 1.05 pF 0.85 pF 240.00 pF 310.00 pF
v5.1
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SX-A Family FPGAs
Guidelines for Estimating Power
The following guidelines are meant to represent worst-case scenarios; they can be generally used to predict the upper limits of power dissipation: Logic Modules (m) = 20% of modules Inputs Switching (n) = Number inputs/4 Outputs Switching (p) = Number of outputs/4 CLKA Loads (q1) = 20% of R-cells CLKB Loads (q2) = 20% of R-cells Load Capacitance (CL) = 35 pF Average Logic Module Switching Rate (fm) = f/10 Average Input Switching Rate (fn) =f/5 Average Output Switching Rate (fp) = f/10 Average CLKA Rate (fq1) = f/2 Average CLKB Rate (fq2) = f/2 Average HCLK Rate (fs1) = f HCLK loads (s1) = 20% of R-cells To assist customers in estimating the power dissipations of their designs, Actel has published the eX, SX-A and RT54SX-S Power Calculator worksheet.
2 -1 0
v5.1
SX-A Family FPGAs
Thermal Characteristics
Introduction
The temperature variable in Actel Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's junction to be higher than the ambient, case, or board temperatures. EQ 2-9 and EQ 2-10 give the relationship between thermal resistance, temperature gradient and power. TJ - TA JA = ---------------P
EQ 2-9
TC - TA JA = ----------------P
EQ 2-10
Where:
JA = Junction-to-air thermal resistance JC = Junction-to-case thermal resistance TJ TA TC P = Junction temperature = Ambient temperature = Ambient temperature = total power dissipated by the device
Table 2-12 * Package Thermal Characteristics JA Package Type Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP)
1
Pin Count 100 144 176 208 Spreader2 208 329 144 256 484
JC 14 11 11 8 3.8 3 3.8 3.8 3.2
Still Air 33.5 33.5 24.7 26.1 16.2 17.1 26.9 26.6 18
1.0 m/s 2.5 m/s 200 ft./min. 500 ft./min. 27.4 28 19.9 22.5 13.3 13.8 22.9 22.8 14.7 25 25.7 18 20.8 11.9 12.8 21.5 21.5 13.6
Units C/W C/W C/W C/W C/W C/W C/W C/W C/W
Plastic Quad Flat Pack (PQFP) with Heat Plastic Ball Grid Array (PBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Notes:
1. The A54SX08A PQ208 has no heat spreader. 2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A.
v5.1
2-11
SX-A Family FPGAs
Theta-JA
Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by JESD-51 series but has little relevance in actual performance of the product in real application. It should be employed with caution but is useful for comparing the thermal performance of one package to another. A sample calculation to estimate the absolute maximum power dissipation allowed (worst case) for a 329-pin PBGA package at still air is as follows. i.e.: JA = 17.1C/W is taken from Table 2-12 on page 2-11 TA = 125C is the maximum limit of ambient (from the datasheet)
150C - 125C Max Junction Temp - Max. Ambient Temp Max. Allowed Power = ----------------------------------------------------------------------------------------------------------- = --------------------------------------- = 1.46 W 17.1C/W JA
EQ 2-11
The device's power consumption must be lower than the calculated maximum power dissipation by the package. The power consumption of a device can be calculated using the Actel power calculator. If the power consumption is higher than the device's maximum allowable power dissipation, then a heat sink can be attached on top of the case or the airflow inside the system must be increased.
Theta-JC
Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the surface of the chip to the top or bottom surface of the package. It is applicable for packages used with external heat sinks and only applies to situations where all or nearly all of the heat is dissipated through the surface in consideration. If the power consumption is higher than the calculated maximum power dissipation of the package, then a heat sink is required.
Calculation for Heat Sink
For example, in a design implemented in a FG484 package, the power consumption value using the power calculator is 3.00 W. The user-dependent data TJ and TA are given as follows: TJ
= 110C
TA = 70C From the datasheet:
JA = 18.0C/W JC = 3.2 C/W
110C - 70C P = Max Junction Temp - Max. Ambient Temp = ------------------------------------ = 2.22 W ---------------------------------------------------------------------------------------------------------- JA 18.0C/W
EQ 2-12
The 2.22 W power is less than then required 3.00 W; therefore, the design requires a heat sink or the airflow where the device is mounted should be increased. The design's junction-to-air thermal resistance requirement can be estimated by: 110C - 70C JA = Max Junction Temp - Max. Ambient Temp = ------------------------------------ = 13.33C/W ----------------------------------------------------------------------------------------------------------P 3.00 W
EQ 2-13
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v5.1
SX-A Family FPGAs
To determine the heat sink's thermal performance, use the following equation: JA(TOTAL) = JC + CS + SA
EQ 2-14
where: CS = = SA = 0.37C/W thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer thermal resistance of the heat sink in C/W
SA = JA(TOTAL) - JC - CS EQ 2-15 SA = 13.33C/W - 3.20C/W - 0.37C/W SA = 9.76C/W A heat sink with a thermal resistance of 9.76C/W or better should be used. Thermal resistance of heat sinks is a function of airflow. The heat sink performance can be significantly improved with the presence of airflow. Carefully estimating thermal resistance is important in the long-term reliability of an Actel FPGA. Design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device, using the provided thermal resistance data. Note: The values may vary depending on the application.
v5.1
2-13
SX-A Family FPGAs
SX-A Timing Model
Input Delays Internal Delays Combinatorial Cell Predicted Routing Delays Output Delays
I/O Module t INYH = 0.5 ns
t RD1 = 0.3 ns t RD2 = 0.4 ns
I/O Module
t PD = 1.0 ns
t RD1 = 0.3 ns t RD4 = 0.7 ns t RD8 = 1.2 ns I/O Module t DHL = 2.7 ns
t DHL = 2.7 ns
Register Cell
t SUD = 0.7 ns t HD = 0.0 ns Routed Clock
D
Q
t RD1 = 0.3 ns t ENZL= 1.3 ns
t RCKH = 2.6 ns (100% Load)
t RCO= 0.7 ns Register Cell
I/O Module t DHL = 2.7 ns
I/O Module t INYH = 0.5 ns t SUD = 0.7 ns t HD = 0.0 ns Hardwired Clock
D
Q
t RD1 = 0.3 ns t ENZL= 1.3 ns
t HCKH = 1.6 ns
t RCO= 0.7 ns
Note: *Values shown for A54SX72A, -3, worst-case commercial conditions at 5 V PCI with standard place-and-route. Figure 2-3 * SX-A Timing Model
Sample Path Calculations
Hardwired Clock
External Setup = (tINYH + tIRD1 + tSUD) - tHCKH = 0.5 + 0.3 + 0.7 - 1.6 = - 0.1 ns Clock-to-Out (Pad-to-Pad) = tHCKH + tRCO + tRD1 + tDHL = 1.6+0.7+0.3+2.7 = 5.3 ns
Routed Clock
External Setup = (tINYH + tIRD1 + tSUD) - tRCKH = 0.5 + 0.3 + 0.7 - 2.6 = -1.1 ns Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tDHL = 2.6 + 0.7 + 0.3 + 2.7 = 6.3 ns
2 -1 4
v5.1
SX-A Family FPGAs
Output Buffer Delays
E D TRIBUFF PAD To AC Test Loads (shown below)
VCC In Out VOL tDLH
Figure 2-4 * Output Buffer Delays
VCC GND 1.5 V En Out 50% 50% VCC 1.5 V VOL tENZL GND 10% tENLZ En Out GND
VCC 50% 50% 1.5 V tENZH tENHZ GND 90%
50% 50% VOH 1.5 V
AC Test Loads
Load 1 (Used to measure propagation delay) To the Output Under Test 35 pF Load 2 (Used to measure enable delays) VCC GND R to VCC for tPZL R to GND for tPZH R = 1 k 35 pF Load 3 (Used to measure disable delays) VCC GND R to VCC for tPZL R to GND for tPZH R = 1 k 5 pF
To the Output Under Test
To the Output Under Test
Figure 2-5 * AC Test Loads
v5.1
2-15
SX-A Family FPGAs
Input Buffer Delays
Y
C-Cell Delays
S A B VCC S, A, or B
PAD
INBUF
Y
In Out GND
3V 1.5 V 1.5 V VCC 50% tINY tINY
50% 50% VCC 50% tPD 50% tPD tPD
GND 50% VCC 50%
0V 50%
Out GND Out
GND tPD
Figure 2-6 * Input Buffer Delays
Figure 2-7 * C-Cell Delays
Cell Timing Characteristics
D CLK PRESET CLR Q
(Positive Edge Triggered) t HD D t SUD CLK t HPWH t RPWH t RCO Q tCLR CLR t WASYN PRESET tPRESET tHPWL t RPWL tHP
Figure 2-8 * Flip-Flops
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v5.1
SX-A Family FPGAs
Timing Characteristics
Timing characteristics for SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all SX-A family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design are complete. The timing characteristics listed in this datasheet represent sample timing numbers of the SX-A devices. Design-specific delay values may be determined by using Timer or performing simulation after successful place-and-route with the Designer software.
Long Tracks
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout routing delays.
Timing Derating
SX-A devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6 percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical.
Temperature and Voltage Derating Factors
Table 2-13 * Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, TJ = 70C, VCCA = 2.25 V) Junction Temperature (TJ) VCCA 2.250 V 2.500 V 2.750 V -55C 0.79 0.74 0.68 -40C 0.80 0.75 0.69 0C 0.87 0.82 0.75 25C 0.89 0.83 0.77 70C 1.00 0.94 0.87 85C 1.04 0.97 0.90 125C 1.14 1.07 0.99
v5.1
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SX-A Family FPGAs
Timing Characteristics
Table 2-14 * A54SX08A Timing Characteristics (Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -2 Speed Parameter C-Cell Propagation Delays tPD
1
-1 Speed
Std. Speed Min. Max.
-F Speed Min. Max. Units
Description
Min. Max. Min. Max.
Internal Array Module
2
0.9
1.1
1.2
1.7
ns
Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12
FO = 1 Routing Delay, Direct Connect FO = 1 Routing Delay, Fast Connect FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
0.1 0.3 0.3 0.5 0.6 0.8 1.4 2
0.1 0.3 0.4 0.5 0.7 0.9 1.5 2.2
0.1 0.4 0.5 0.6 0.8 1 1.8 2.6
0.1 0.6 0.6 0.8 1.1 1.4 2.5 3.6
ns ns ns ns ns ns ns ns
R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tMPW Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Hold Time Clock Pulse Width 0.7 0.0 1.4 0.4 0.3 1.6 0.7 0.6 0.7 0.8 0.0 1.5 0.4 0.3 1.8 0.8 0.6 0.7 0.9 0.0 1.8 0.5 0.4 2.1 0.9 0.8 0.9 1.2 0.0 2.5 0.7 0.6 2.9 1.3 1.0 1.2 ns ns ns ns ns ns ns ns ns
Input Module Propagation Delays tINYH tINYL tINYH tINYL tINYH tINYL Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Input Data Pad to Y High 2.5 V LVCMOS Input Data Pad to Y Low 2.5 V LVCMOS Input Data Pad to Y High 3.3 V PCI Input Data Pad to Y Low 3.3 V PCI Input Data Pad to Y High 3.3 V LVTTL Input Data Pad to Y Low 3.3 V LVTTL 0.8 1.0 0.6 0.7 0.7 1.0 0.9 1.2 0.6 0.8 0.7 1.1 1.0 1.4 0.7 0.9 0.9 1.3 1.4 1.9 1.0 1.3 1.2 1.8 ns ns ns ns ns ns
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SX-A Family FPGAs
Table 2-14 * A54SX08A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -2 Speed Parameter tINYH tINYL tINYH tINYL Description Input Data Pad to Y High 5 V PCI Input Data Pad to Y Low 5 V PCI Input Data Pad to Y High 5 V TTL Input Data Pad to Y Low 5 V TTL
2
-1 Speed
Std. Speed Min. Max. 0.7 1.1 0.7 1.1
-F Speed Min. Max. Units 0.9 1.5 0.9 1.5 ns ns ns ns
Min. Max. Min. Max. 0.5 0.8 0.5 0.8 0.6 0.9 0.6 0.9
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes: FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
0.3 0.5 0.6 0.8 1.4 2
0.3 0.5 0.7 0.9 1.5 2.2
0.4 0.6 0.8 1 1.8 2.6
0.6 0.8 1.1 1.4 2.5 3.6
ns ns ns ns ns ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.1
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SX-A Family FPGAs
Table 2-15 * A54SX08A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70C) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std. Speed Min. Max. -F Speed Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 3.2 313 1.6 1.6 0.4 3.6 278 1.4 1.3 1.8 1.8 0.4 4.2 238 1.6 1.5 2.1 2.1 0.5 5.8 172 1.8 1.7 2.9 2.9 0.7 2.6 2.4 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.6 1.6 0.7 0.7 0.9 1.0 1.1 1.0 1.1 1.1 1.3 1.8 1.8 0.8 0.8 1.0 1.1 1.2 1.1 1.2 1.2 1.5 2.1 2.1 0.9 0.9 1.2 1.3 1.4 1.3 1.4 1.4 1.7 2.9 2.9 1.3 1.3 1.7 1.8 2.0 1.8 2.0 2.0 2.4 ns ns ns ns ns ns ns ns ns ns ns
2 -2 0
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SX-A Family FPGAs
Table 2-16 * A54SX08A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std. Speed Min. Max. -F Speed Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 3.2 313 1.6 1.6 0.4 3.6 278 1.3 1.1 1.8 1.8 0.5 4.2 238 1.5 1.3 2.1 2.1 0.5 5.8 172 1.7 1.5 2.9 2.9 0.8 2.6 2.2 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.6 1.6 0.7 0.7 0.8 0.8 1.1 0.8 1.1 1.1 1.2 1.8 1.8 0.8 0.8 0.9 0.9 1.2 0.9 1.2 1.2 1.3 2.1 2.1 0.9 0.9 1.1 1.1 1.4 1.1 1.4 1.4 1.6 2.9 2.9 1.3 1.3 1.5 1.5 2 1.5 2 1.9 2.2 ns ns ns ns ns ns ns ns ns ns ns
v5.1
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SX-A Family FPGAs
Table 2-17 * A54SX08A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70C) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std. Speed Min. Max. -F Speed Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 3.2 313 1.6 1.6 0.4 3.6 278 1.2 1.0 1.8 1.8 0.4 4.2 238 1.3 1.2 2.1 2.1 0.5 5.8 172 1.5 1.4 2.9 2.9 0.8 2.3 2.0 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.6 1.6 0.8 0.8 0.9 0.9 1.5 0.9 1.5 1.1 1.6 1.8 1.8 0.9 1.0 1.0 1.0 1.7 1.0 1.7 1.3 1.8 2.1 2.1 1.1 1.1 1.2 1.2 2.0 1.2 2.0 1.5 2.1 2.9 2.9 1.5 1.5 1.7 1.7 2.7 1.7 2.7 2.1 2.9 ns ns ns ns ns ns ns ns ns ns ns
2 -2 2
v5.1
SX-A Family FPGAs
Table 2-18 * A54SX08A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3V, TJ = 70C) -2 Speed Parameter Description Timing1,2 3.9 3.0 13.3 2.8 13.7 3.9 2.5 3.0 0.037 0.017 0.06 4.4 3.4 15.1 3.2 15.5 4.4 2.8 3.4 0.043 0.023 0.071 5.2 3.9 17.7 3.7 18.2 5.2 3.3 3.9 0.051 0.023 0.086 7.2 5.5 24.8 5.2 25.5 7.2 4.7 5.5 0.071 0.037 0.117 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF Min. Max. -1 Speed Min. Max. Std. Speed Min. Max. -F Speed Min. Max. Units
2.5 V LVCMOS Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH3 dTHL3 dTHLS
3
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Data-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
Note: 1. Delays based on 35 pF loading. 2. The equivalent I/O Attribute Editor settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software. 3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
v5.1
2-23
SX-A Family FPGAs
Table 2-19 * A54SX08A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -2 Speed Parameter 3.3 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2 Description Timing1 2.2 2.3 1.7 2.2 2.8 2.3 0.03 0.015 2.4 2.6 1.9 2.4 3.2 2.6 0.03 0.015 2.9 3.1 2.2 2.9 3.8 3.1 0.04 0.015 4.0 4.3 3.1 4.0 5.3 4.3 0.045 0.025 ns ns ns ns ns ns ns/pF ns/pF Min. Max. -1 Speed Min. Max. Std. Speed Min. Max. -F Speed Min. Max. Units
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
3.3 V LVTTL Output Module Timing3 tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH2 dTHL2 dTHLS
2
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
3.0 3.0 10.4 2.6 18.9 3 3.3 3 0.03 0.015 0.053
3.4 3.3 11.8 2.9 21.3 3.4 3.7 3.3 0.03 0.015 0.067
4.0 3.9 13.8 3.4 25.4 4 4.4 3.9 0.04 0.015 0.073
5.6 5.5 19.3 4.8 34.9 5.6 6.2 5.5 0.045 0.025 0.107
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading.
2 -2 4
v5.1
SX-A Family FPGAs
Table 2-20 * A54SX08A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70C) -2 Speed Parameter 5 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2 Description Timing1 2.4 3.2 1.5 2.4 3.5 3.2 0.016 0.03 2.8 3.6 1.7 2.8 3.9 3.6 0.02 0.032 3.2 4.2 2.0 3.2 4.6 4.2 0.022 0.04 4.5 5.9 2.8 4.5 6.4 5.9 0.032 0.052 ns ns ns ns ns ns ns/pF ns/pF Min. Max. -1 Speed Min. Max. Std. Speed Min. Max. -F Speed Min. Max. Units
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
5 V TTL Output Module Timing3 tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Notes: 1. Delays based on 50 pF loading. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading. Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew 2.4 3.2 7.6 2.4 8.4 2.4 4.2 3.2 0.017 0.029 0.046 2.8 3.6 8.6 2.7 9.5 2.8 4.7 3.6 0.017 0.031 0.057 3.2 4.2 10.1 3.2 11.0 3.2 5.6 4.2 0.023 0.037 0.066 4.5 5.9 14.2 4.5 15.4 4.5 7.8 5.9 0.031 0.051 0.089 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
v5.1
2-25
SX-A Family FPGAs
Table 2-21 * A54SX16A Timing Characteristics (Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter C-Cell Propagation tPD Description Delays1 0.9 1.0 1.2 1.4 1.9 ns -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Internal Array Module Delays2
Predicted Routing tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12
FO = 1 Routing Delay, Direct Connect FO = 1 Routing Delay, Fast Connect FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
0.1 0.3 0.3 0.4 0.5 0.7 1.2 1.7
0.1 0.3 0.3 0.5 0.6 0.8 1.4 2
0.1 0.3 0.4 0.5 0.7 0.9 1.5 2.2
0.1 0.4 0.5 0.6 0.8 1 1.8 2.6
0.1 0.6 0.6 0.8 1.1 1.4 2.5 3.6
ns ns ns ns ns ns ns ns
R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tMPW Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Clock Minimum Pulse Width 0.7 0.0 1.3 0.3 0.3 1.4 0.6 0.5 0.7 0.8 0.0 1.5 0.4 0.3 1.7 0.7 0.6 0.8 0.9 0.0 1.6 0.4 0.3 1.9 0.8 0.6 0.8 1.0 0.0 1.9 0.5 0.4 2.2 0.9 0.8 1.0 1.4 0.0 2.7 0.7 0.6 3.0 1.3 1.0 1.4 ns ns ns ns ns ns ns ns ns
Input Module Propagation Delays tINYH tINYL tINYH tINYL tINYH tINYL tINYH Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Input Data Pad to Y High 2.5 V LVCMOS Input Data Pad to Y Low 2.5 V LVCMOS Input Data Pad to Y High 3.3 V PCI Input Data Pad to Y Low 3.3 V PCI Input Data Pad to Y High 3.3 V LVTTL Input Data Pad to Y Low 3.3 V LVTTL Input Data Pad to Y High 5 V PCI 0.5 0.8 0.5 0.7 0.7 0.9 0.5 0.6 0.9 0.6 0.8 0.7 1.1 0.5 0.7 1.0 0.6 0.9 0.8 1.2 0.6 0.8 1.1 0.7 1.0 1.0 1.4 0.7 1.1 1.6 1.0 1.4 1.4 2.0 0.9 ns ns ns ns ns ns ns
2 -2 6
v5.1
SX-A Family FPGAs
Table 2-21 * A54SX16A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter tINYL tINYH tINYL Description Input Data Pad to Y Low 5 V PCI Input Data Pad to Y High 5 V TTL Input Data Pad to Y Low 5 V TTL
2
-2 Speed
-1 Speed
Std. Speed
-F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 0.7 0.5 0.7 0.8 0.5 0.8 0.9 0.6 0.9 1.1 0.7 1.1 1.5 0.9 1.5 ns ns ns
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes: FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
0.3 0.4 0.5 0.7 1.2 1.7
0.3 0.5 0.6 0.8 1.4 2.0
0.3 0.5 0.7 0.9 1.5 2.2
0.4 0.6 0.8 1.0 0.8 2.6
0.6 0.8 1.1 1.4 2.5 3.6
ns ns ns ns ns ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.1
2-27
SX-A Family FPGAs
Table 2-22 * A54SX16A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 0.3 3.4 294 1.2 1.0 1.7 1.7 0.3 3.8 263 1.4 1.1 1.9 1.9 0.4 4.4 227 1.6 1.2 2.2 2.2 0.4 6.0 167 1.8 1.5 3.0 3.0 0.7 2.8 2.2 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.4 1.4 0.8 0.8 1.0 1.0 1.1 1.1 1.1 1.3 1.3 1.7 1.7 0.9 0.9 1.1 1.2 1.3 1.3 1.3 1.5 1.5 1.9 1.9 1.0 1.0 1.3 1.3 1.5 1.5 1.5 1.7 1.7 2.2 2.2 1.2 1.2 1.5 1.6 1.7 1.7 1.7 2.0 2.0 3.0 3.0 1.7 1.7 2.1 2.2 2.4 2.4 2.4 2.8 2.8 ns ns ns ns ns ns ns ns ns ns ns
2 -2 8
v5.1
SX-A Family FPGAs
Table 2-23 * A54SX16A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 0.3 3.4 294 1.2 1.0 1.7 1.7 0.3 3.8 263 1.4 1.1 1.9 1.9 0.4 4.4 227 1.6 1.3 2.2 2.2 0.4 6.0 167 1.8 1.5 3.0 3.0 0.6 2.8 2.2 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.4 1.4 0.8 0.8 1.0 1.0 1.1 1.1 1.1 1.3 1.3 1.7 1.7 0.9 0.9 1.1 1.2 1.3 1.3 1.3 1.5 1.5 1.9 1.9 1.0 1.0 1.3 1.3 1.5 1.4 1.5 1.7 1.7 2.2 2.2 1.2 1.2 1.5 1.5 1.7 1.7 1.7 2.0 2.0 3.0 3.0 1.7 1.7 2.1 2.1 2.4 2.3 2.4 2.7 2.8 ns ns ns ns ns ns ns ns ns ns ns
v5.1
2-29
SX-A Family FPGAs
Table 2-24 * A54SX16A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI =4.75 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 0.3 3.4 294 1.2 1.0 1.7 1.7 0.3 3.8 263 1.4 1.1 1.9 1.9 0.4 4.4 227 1.6 1.2 2.2 2.2 0.4 6.0 167 1.8 1.5 3.0 3.0 0.7 2.8 2.2 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.4 1.4 0.8 0.8 1.0 1.0 1.1 1.1 1.1 1.3 1.3 1.7 1.7 0.9 0.9 1.1 1.2 1.3 1.3 1.3 1.5 1.5 1.9 1.9 1.0 1.0 1.3 1.3 1.5 1.5 1.5 1.7 1.7 2.2 2.2 1.2 1.2 1.5 1.6 1.7 1.7 1.7 2.0 2.0 3.0 3.0 1.7 1.7 2.1 2.2 2.4 2.4 2.4 2.8 2.8 ns ns ns ns ns ns ns ns ns ns ns
2 -3 0
v5.1
SX-A Family FPGAs
Table 2-25 * A54SX16A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70C) -3 Speed Parameter Description Timing 1, 2 3.4 2.6 11.6 2.4 11.8 3.4 2.1 2.6 0.031 0.017 0.057 3.9 3.0 13.4 2.8 13.7 3.9 2.5 3.0 0.037 0.017 0.06 4.5 3.3 15.2 3.2 15.5 4.5 2.8 3.3 0.043 0.023 0.071 5.2 3.9 17.9 3.7 18.2 5.2 3.3 3.9 0.051 0.023 0.086 7.3 5.5 25.0 5.2 25.5 7.3 4.7 5.5 0.071 0.037 0.117 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2.5 V LVCMOS Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH3 dTHL3 dTHLS
3
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Data-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
Note: 1. Delays based on 35 pF loading. 2. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software. 3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
v5.1
2-31
SX-A Family FPGAs
Table 2-26 * A54SX16A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter Description Timing1 2.0 2.2 1.4 2.0 2.5 2.2 0.025 0.015 2.3 2.5 1.7 2.3 2.8 2.5 0.03 0.015 2.6 2.8 1.9 2.6 3.2 2.8 0.03 0.015 3.1 3.3 2.2 3.1 3.8 3.3 0.04 0.015 4.3 4.6 3.1 4.3 5.3 4.6 0.045 0.025 ns ns ns ns ns ns ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
3.3 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
3.3 V LVTTL Output Module Timing3 tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH2 dTHL2 dTHLS
2
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
2.8 2.7 9.5 2.2 15.8 2.8 2.9 2.7 0.025 0.015 0.053
3.2 3.1 10.9 2.6 18.9 3.2 3.3 3.1 0.03 0.015 0.053
3.6 3.5 12.4 2.9 21.3 3.6 3.7 3.5 0.03 0.015 0.067
4.3 4.1 14.6 3.4 25.4 4.3 4.4 4.1 0.04 0.015 0.073
6.0 5.7 20.4 4.8 34.9 6.0 6.2 5.7 0.045 0.025 0.107
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading.
2 -3 2
v5.1
SX-A Family FPGAs
Table 2-27 * A54SX16A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70C) -3 Speed Parameter Description Timing1 2.2 2.8 1.3 2.2 3.0 2.8 0.016 0.026 2.5 3.2 1.5 2.5 3.5 3.2 0.016 0.03 2.8 3.6 1.7 2.8 3.9 3.6 0.02 0.032 3.3 4.2 2.0 3.3 4.6 4.2 0.022 0.04 4.6 5.9 2.8 4.6 6.4 5.9 0.032 0.052 ns ns ns ns ns ns ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
5 V TTL Output Module Timing3 tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH2 dTHL2 dTHLS
2
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
2.2 2.8 6.7 2.1 7.4 1.9 3.6 2.5 0.014 0.023 0.043
2.5 3.2 7.7 2.4 8.4 2.2 4.2 2.9 0.017 0.029 0.046
2.8 3.6 8.7 2.7 9.5 2.5 4.7 3.3 0.017 0.031 0.057
3.3 4.2 10.2 3.2 11.0 2.9 5.6 3.9 0.023 0.037 0.066
4.6 5.9 14.3 4.5 15.4 4.1 7.8 5.4 0.031 0.051 0.089
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
Notes: 1. Delays based on 50 pF loading. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading.
v5.1
2-33
SX-A Family FPGAs
Table 2-28 * A54SX32A Timing Characteristics (Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter C-Cell Propagation tPD Description Delays1 0.8 0.9 1.1 1.2 1.7 ns -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Internal Array Module Delays2
Predicted Routing tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12
FO = 1 Routing Delay, Direct Connect FO = 1 Routing Delay, Fast Connect FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
0.1 0.3 0.3 0.4 0.5 0.7 1.2 1.7
0.1 0.3 0.3 0.5 0.6 0.8 1.4 2.0
0.1 0.3 0.4 0.5 0.7 0.9 1.5 2.2
0.1 0.4 0.5 0.6 0.8 1.0 1.8 2.6
0.1 0.6 0.6 0.8 1.1 1.4 2.5 3.6
ns ns ns ns ns ns ns ns
R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tMPW Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Clock Pulse Width 0.6 0.0 1.2 0.3 0.3 1.4 0.6 0.5 0.6 0.7 0.0 1.4 0.4 0.3 1.6 0.7 0.6 0.7 0.8 0.0 1.5 0.4 0.3 1.8 0.8 0.6 0.7 0.9 0.0 1.8 0.5 0.4 2.1 0.9 0.8 0.9 1.2 0.0 2.5 0.7 0.6 2.9 1.3 1.0 1.2 ns ns ns ns ns ns ns ns ns
Input Module Propagation Delays tINYH tINYL tINYH tINYL tINYH tINYL tINYH Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Input Data Pad to Y High 2.5 V LVCMOS Input Data Pad to Y Low 2.5 V LVCMOS Input Data Pad to Y High 3.3 V PCI Input Data Pad to Y Low 3.3 V PCI Input Data Pad to Y High 3.3 V LVTTL Input Data Pad to Y Low 3.3 V LVTTL Input Data Pad to Y High 5 V PCI 0.6 1.2 0.5 0.6 0.8 1.4 0.7 0.7 1.3 0.6 0.7 0.9 1.6 0.8 0.8 1.5 0.6 0.8 1.0 1.8 0.9 0.9 1.8 0.7 0.9 1.2 2.2 1.0 1.2 2.5 1.0 1.3 1.6 3.0 1.4 ns ns ns ns ns ns ns
2 -3 4
v5.1
SX-A Family FPGAs
Table 2-28 * A54SX32A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter tINYL tINYH tINYL Description Input Data Pad to Y Low 5 V PCI Input Data Pad to Y High 5 V TTL Input Data Pad to Y Low 5 V TTL
2
-2 Speed
-1 Speed
Std. Speed
-F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 0.9 0.9 1.4 1.1 1.1 1.6 1.2 1.2 1.8 1.4 1.4 2.1 1.9 1.9 2.9 ns ns ns
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes: FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
0.3 0.4 0.5 0.7 1.2 1.7
0.3 0.5 0.6 0.8 1.4 2
0.3 0.5 0.7 0.9 1.5 2.2
0.4 0.6 0.8 1 1.8 2.6
0.6 0.8 1.1 1.4 2.5 3.6
ns ns ns ns ns ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.1
2-35
SX-A Family FPGAs
Table 2-29 * A54SX32A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 0.6 3.2 313 1.7 1.7 1.6 1.6 0.6 3.6 278 2.0 2.0 1.8 1.8 0.7 4.2 238 2.2 2.2 2.1 2.1 0.8 5.8 172 2.6 2.6 2.9 2.9 1.3 4.0 4.0 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.4 1.4 1.0 0.9 0.9 2.2 2.1 2.4 2.2 2.5 2.4 1.6 1.6 1.1 1.0 1.0 2.5 2.4 2.7 2.5 2.9 2.7 1.8 1.8 1.3 1.2 1.2 2.9 2.7 3.1 2.8 3.2 3.1 2.1 2.1 1.5 1.4 1.4 3.4 3.2 3.6 3.3 3.8 3.6 2.9 2.9 2.1 1.9 1.9 4.7 4.4 5.1 4.6 5.3 5.0 ns ns ns ns ns ns ns ns ns ns ns
2 -3 6
v5.1
SX-A Family FPGAs
Table 2-30 * A54SX32A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 0.6 3.2 313 1.7 1.7 1.6 1.6 0.6 3.6 278 2.0 2.0 1.8 1.8 0.7 4.2 238 2.2 2.2 2.1 2.1 0.8 5.8 172 2.6 2.6 2.9 2.9 1.3 4.0 4.0 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.4 1.4 1.0 0.9 0.9 2.2 2.1 2.3 2.2 2.4 2.4 1.6 1.6 1.1 1.0 1.0 2.5 2.4 2.7 2.5 2.8 2.8 1.8 1.8 1.3 1.2 1.2 2.8 2.7 3.1 2.9 3.2 3.1 2.1 2.1 1.5 1.4 1.4 3.3 3.2 3.6 3.4 3.7 3.7 2.9 2.9 2.1 1.9 1.9 4.6 4.5 5 4.7 5.2 5.1 ns ns ns ns ns ns ns ns ns ns ns
v5.1
2-37
SX-A Family FPGAs
Table 2-31 * A54SX32A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 0.6 3.2 313 1.7 1.7 1.6 1.6 0.6 3.6 278 1.9 2.0 1.8 1.8 0.7 4.2 238 2.2 2.2 2.1 2.1 0.8 5.8 172 2.6 2.6 2.9 2.9 1.3 4.0 4.0 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.4 1.4 1.0 1.0 1.0 2.2 2.1 2.4 2.2 2.5 2.4 1.6 1.6 1.1 1.1 1.1 2.5 2.5 2.7 2.6 2.8 2.8 1.8 1.8 1.3 1.3 1.3 2.8 2.8 3.1 2.9 3.2 3.1 2.1 2.1 1.5 1.5 1.5 3.3 3.3 3.6 3.4 3.8 3.7 2.9 2.9 2.1 2.1 2.1 4.7 4.5 5.1 4.7 5.3 5.2 ns ns ns ns ns ns ns ns ns ns ns
2 -3 8
v5.1
SX-A Family FPGAs
Table 2-32 * A54SX32A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3V, TJ = 70C) -3 Speed Parameter Description Timing 1,2 3.3 2.5 11.1 2.4 11.8 3.3 2.1 2.5 0.031 0.017 0.057 3.8 2.9 12.8 2.8 13.7 3.8 2.5 2.9 0.037 0.017 0.06 4.2 3.2 14.5 3.2 15.5 4.2 2.8 3.2 0.043 0.023 0.071 5.0 3.8 17.0 3.7 18.2 5.0 3.3 3.8 0.051 0.023 0.086 7.0 5.3 23.8 5.2 25.5 7.0 4.7 5.3 0.071 0.037 0.117 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2.5 V LVCMOS Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH3 dTHL3 dTHLS
3
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Data-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
Note: 1. Delays based on 35 pF loading. 2. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software. 3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
v5.1
2-39
SX-A Family FPGAs
Table 2-33 * A54SX32A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter Description Timing1 1.9 2.0 1.4 1.9 2.5 2.0 0.025 0.015 2.2 2.3 1.7 2.2 2.8 2.3 0.03 0.015 2.4 2.6 1.9 2.4 3.2 2.6 0.03 0.015 2.9 3.1 2.2 2.9 3.8 3.1 0.04 0.015 4.0 4.3 3.1 4.0 5.3 4.3 0.045 0.025 ns ns ns ns ns ns ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
3.3 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
3.3 V LVTTL Output Module Timing3 tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH2 dTHL2 dTHLS
2
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
2.6 2.6 9.0 2.2 15.8 2.6 2.9 2.6 0.025 0.015 0.053
3.0 3.0 10.4 2.6 18.9 3.0 3.3 3.0 0.03 0.015 0.053
3.4 3.3 11.8 2.9 21.3 3.4 3.7 3.3 0.03 0.015 0.067
4.0 3.9 13.8 3.4 25.4 4.0 4.4 3.9 0.04 0.015 0.073
5.6 5.5 19.3 4.8 34.9 5.6 6.2 5.5 0.045 0.025 0.107
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading.
2 -4 0
v5.1
SX-A Family FPGAs
Table 2-34 * A54SX32A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70C) -3 Speed Parameter Description Timing1 2.1 2.8 1.3 2.1 3.0 2.8 0.016 0.026 2.4 3.2 1.5 2.4 3.5 3.2 0.016 0.03 2.8 3.6 1.7 2.8 3.9 3.6 0.02 0.032 3.2 4.2 2.0 3.2 4.6 4.2 0.022 0.04 4.5 5.9 2.8 4.5 6.4 5.9 0.032 0.052 ns ns ns ns ns ns ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
5 V TTL Output Module Timing3 tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH2 dTHL2 dTHLS
2
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
1.9 2.5 6.6 2.1 7.4 1.9 3.6 2.5 0.014 0.023 0.043
2.2 2.9 7.6 2.4 8.4 2.2 4.2 2.9 0.017 0.029 0.046
2.5 3.3 8.6 2.7 9.5 2.5 4.7 3.3 0.017 0.031 0.057
2.9 3.9 10.1 3.2 11.0 2.9 5.6 3.9 0.023 0.037 0.066
4.1 5.4 14.2 4.5 15.4 4.1 7.8 5.4 0.031 0.051 0.089
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
Notes: 1. Delays based on 50 pF loading. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading.
v5.1
2-41
SX-A Family FPGAs
Table 2-35 * A54SX72A Timing Characteristics (Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter C-Cell Propagation tPD Description Delays1 1.0 1.1 1.3 1.5 2.0 ns -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Internal Array Module Delays2
Predicted Routing tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12
FO = 1 Routing Delay, Direct Connect FO = 1 Routing Delay, Fast Connect FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay
0.1 0.3 0.3 0.4 0.5 0.7 1.2 1.7
0.1 0.3 0.3 0.5 0.7 0.9 1.5 2.2
0.1 0.3 0.4 0.6 0.8 1 1.7 2.5
0.1 0.4 0.5 0.7 0.9 1.1 2.1 3
0.1 0.6 0.7 1 1.3 1.5 2.9 4.2
ns ns ns ns ns ns ns ns
R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tMPW Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Hold Time Clock Minimum Pulse Width 0.7 0.0 1.3 0.3 0.3 1.5 0.7 0.6 0.7 0.8 0.0 1.5 0.4 0.3 1.7 0.8 0.7 0.8 0.9 0.0 1.7 0.4 0.3 2.0 0.9 0.7 0.8 1.0 0.0 2.0 0.5 0.4 2.3 1.1 0.9 1.0 1.4 0.0 2.8 0.7 0.6 3.2 1.5 1.2 1.4 ns ns ns ns ns ns ns ns ns
Input Module Propagation Delays tINYH tINYL tINYH tINYL tINYH tINYL tINYH Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. Input Data Pad to Y High 2.5 V LVCMOS Input Data Pad to Y Low 2.5 V LVCMOS Input Data Pad to Y High 3.3 V PCI Input Data Pad to Y Low 3.3 V PCI Input Data Pad to Y High 3.3 V LVTTL Input Data Pad to Y Low 3.3 V LVTTL Input Data Pad to Y High 5 V PCI 0.6 0.8 0.6 0.7 0.7 1.0 0.5 0.7 1.0 0.7 0.8 0.7 1.2 0.6 0.8 1.1 0.7 0.9 0.8 1.3 0.7 0.9 1.3 0.9 1.0 1.0 1.5 0.8 1.3 1.7 1.2 1.4 1.4 2.1 1.1 ns ns ns ns ns ns ns
2 -4 2
v5.1
SX-A Family FPGAs
Table 2-35 * A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter tINYL tINYH tINYL Description Input Data Pad to Y Low 5 V PCI Input Data Pad to Y High 5 V TTL Input Data Pad to Y Low 5 V TTL -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 0.8 0.7 0.9 0.9 0.8 1.1 1.0 0.9 1.2 1.2 1.0 1.4 1.6 1.4 1.9 ns ns ns
Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. FO = 1 Routing Delay FO = 2 Routing Delay FO = 3 Routing Delay FO = 4 Routing Delay FO = 8 Routing Delay FO = 12 Routing Delay 0.3 0.4 0.5 0.7 1.2 1.7 0.3 0.5 0.7 0.9 1.5 2.2 0.4 0.6 0.8 1 1.7 2.5 0.5 0.7 0.9 1.1 2.1 3 0.7 1 1.3 1.5 2.9 4.2 ns ns ns ns ns ns
v5.1
2-43
SX-A Family FPGAs
Table 2-36 * A54SX72A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 3.0 333 1.5 1.5 1.4 3.4 294 1.6 1.6 1.7 1.7 1.6 4.0 250 1.9 1.9 2.0 2.0 1.8 4.6 217 2.1 2.1 2.3 2.3 2.1 6.4 156 2.5 2.5 3.2 3.2 3.3 3.8 3.8 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.5 1.5 1.9 1.8 1.8 2.3 2.8 2.4 2.9 2.6 3.1 1.7 1.7 2.2 2.1 2.1 2.6 3.2 2.8 3.3 3.0 3.6 2.0 2.0 2.5 2.4 2.4 2.9 3.7 3.2 3.8 3.4 4.0 2.3 2.3 3.0 2.8 2.8 3.4 4.3 3.7 4.5 4.0 4.7 3.2 3.2 4.1 3.9 3.9 4.8 6.0 5.2 6.2 5.6 6.6 ns ns ns ns ns ns ns ns ns ns ns
Quadrant Array Clock Networks tQCKH tQCHKL tQCKH tQCHKL tQCKH Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) 2.6 2.6 2.8 2.8 3.0 3.0 3.0 3.2 3.2 3.4 3.4 3.3 3.6 3.6 3.9 4.0 3.9 4.3 4.2 4.6 5.6 5.5 6.0 5.9 6.4 ns ns ns ns ns
2 -4 4
v5.1
SX-A Family FPGAs
Table 2-36 * A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70C) -3 Speed Parameter tQCHKL tQPWH tQPWL tQCKSW tQCKSW tQCKSW Description Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.5 1.5 0.2 0.4 0.4 -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.9 1.7 1.7 0.3 0.5 0.5 3.4 2.0 2.0 0.3 0.5 0.5 3.8 2.3 2.3 0.3 0.6 0.6 4.5 3.2 3.2 0.5 0.9 0.9 6.3 ns ns ns ns ns ns
v5.1
2-45
SX-A Family FPGAs
Table 2-37 * A54SX72A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 3.0 333 1.5 1.5 1.4 3.4 294 1.6 1.7 1.7 1.7 1.6 4.0 250 1.9 1.9 2.0 2.0 1.8 4.6 217 2.1 2.1 2.3 2.3 2.1 6.4 156 2.5 2.5 3.2 3.2 3.3 3.8 3.8 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.5 1.5 1.9 1.9 1.9 2.2 2.8 2.4 2.9 2.6 3.1 1.7 1.7 2.2 2.1 2.1 2.6 3.3 2.8 3.4 3.0 3.6 2.0 2.0 2.5 2.4 2.4 2.9 3.7 3.2 3.8 3.4 4.1 2.3 2.3 3 2.8 2.8 3.4 4.3 3.7 4.5 4.0 4.8 3.2 3.2 4.1 3.9 3.9 4.8 6.0 5.2 6.2 5.6 6.7 ns ns ns ns ns ns ns ns ns ns ns
Quadrant Array Clock Networks tQCKH tQCHKL tQCKH tQCHKL tQCKH Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) 1.3 1.3 1.5 1.5 1.7 1.5 1.5 1.7 1.8 1.9 1.7 1.7 1.9 2 2.2 1.9 2 2.2 2.3 2.5 2.7 2.8 3.1 3.2 3.5 ns ns ns ns ns
2 -4 6
v5.1
SX-A Family FPGAs
Table 2-37 * A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter tQCHKL tQPWH tQPWL tQCKSW tQCKSW tQCKSW Description Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.5 1.5 0.2 0.4 0.4 -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.7 1.7 1.7 0.3 0.5 0.5 2 2.0 2.0 0.3 0.5 0.5 2.2 2.3 2.3 0.3 0.6 0.6 2.6 3.2 3.2 0.5 0.9 0.9 3.6 ns ns ns ns ns ns
v5.1
2-47
SX-A Family FPGAs
Table 2-38 * A54SX72A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70C) -3 Speed Parameter Description -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to R-cell Input) Input High to Low (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 3.0 333 1.5 1.5 1.4 3.4 294 1.6 1.6 1.7 1.7 1.6 4.0 250 1.8 1.9 2.0 2.0 1.8 4.6 217 2.1 2.1 2.3 2.3 2.1 6.4 156 2.4 2.5 3.2 3.2 3.3 3.8 3.8 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.5 1.5 1.9 1.9 1.9 2.3 2.8 2.5 3.0 2.6 3.2 1.7 1.7 2.2 2.2 2.2 2.6 3.2 2.9 3.4 3.0 3.6 2.0 2.0 2.5 2.5 2.5 3.0 3.6 3.2 3.9 3.4 4.1 2.3 2.3 3.0 3.0 3.0 3.5 4.3 3.8 4.6 3.9 4.8 3.2 3.2 4.1 4.1 4.1 4.9 6.0 5.3 6.4 5.5 6.8 ns ns ns ns ns ns ns ns ns ns ns
Quadrant Array Clock Networks tQCKH tQCHKL tQCKH tQCHKL tQCKH Input Low to High (Light Load) (Pad to R-cell Input) Input High to Low (Light Load) (Pad to R-cell Input) Input Low to High (50% Load) (Pad to R-cell Input) Input High to Low (50% Load) (Pad to R-cell Input) Input Low to High (100% Load) (Pad to R-cell Input) 1.2 1.3 1.4 1.4 1.6 1.4 1.4 1.6 1.7 1.8 1.6 1.6 1.8 1.9 2.1 1.8 1.9 2.1 2.2 2.4 2.6 2.7 3.0 3.1 3.4 ns ns ns ns ns
2 -4 8
v5.1
SX-A Family FPGAs
Table 2-38 * A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70C) -3 Speed Parameter tQCHKL tQPWH tQPWL tQCKSW tQCKSW tQCKSW Description Input High to Low (100% Load) (Pad to R-cell Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.5 1.5 0.2 0.4 0.4 -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.6 1.7 1.7 0.3 0.5 0.5 1.9 2.0 2.0 0.3 0.5 0.5 2.1 2.3 2.3 0.3 0.6 0.6 2.5 3.2 3.2 0.5 0.9 0.9 3.5 ns ns ns ns ns ns
v5.1
2-49
SX-A Family FPGAs
Table 2-39 * A54SX72A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3V, TJ = 70C) -3 Speed Parameter Description Timing1, 2 3.9 3.1 12.7 2.4 11.8 3.9 2.1 3.1 0.031 0.017 0.057 4.5 3.6 14.6 2.8 13.7 4.5 2.5 3.6 0.037 0.017 0.06 5.1 4.1 16.5 3.2 15.5 5.1 2.8 4.1 0.043 0.023 0.071 6.0 4.8 19.4 3.7 18.2 6.0 3.3 4.8 0.051 0.023 0.086 8.4 6.7 27.2 5.2 25.5 8.4 4.7 6.7 0.071 0.037 0.117 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2.5 V LVCMOS Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH3 dTHL3 dTHLS
3
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Data-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
Note: 1. Delays based on 35 pF loading. 2. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software. 3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
2 -5 0
v5.1
SX-A Family FPGAs
Table 2-40 * A54SX72A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70C) -3 Speed Parameter Description Timing1 2.3 2.5 1.4 2.3 2.5 2.5 0.025 0.015 2.7 2.9 1.7 2.7 2.8 2.9 0.03 0.015 3.0 3.2 1.9 3.0 3.2 3.2 0.03 0.015 3.6 3.8 2.2 3.6 3.8 3.8 0.04 0.015 5.0 5.3 3.1 5.0 5.3 5.3 0.045 0.025 ns ns ns ns ns ns ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
3.3 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
3.3 V LVTTL Output Module Timing3 tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH2 dTHL2 dTHLS
2
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
3.2 3.2 10.3 2.2 15.8 3.2 2.9 3.2 0.025 0.015 0.053
3.7 3.7 11.9 2.6 18.9 3.7 3.3 3.7 0.03 0.015 0.053
4.2 4.2 13.5 2.9 21.3 4.2 3.7 4.2 0.03 0.015 0.067
5.0 4.9 15.8 3.4 25.4 5.0 4.4 4.9 0.04 0.015 0.073
6.9 6.9 22.2 4.8 34.9 6.9 6.2 6.9 0.045 0.025 0.107
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
Notes: 1. Delays based on 10 pF loading and 25 resistance. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading.
v5.1
2-51
SX-A Family FPGAs
Table 2-41 * A54SX72A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70C) -3 Speed Parameter Description Timing1 2.7 3.4 1.3 2.7 3.0 3.4 0.016 0.026 3.1 3.9 1.5 3.1 3.5 3.9 0.016 0.03 3.5 4.4 1.7 3.5 3.9 4.4 0.02 0.032 4.1 5.1 2.0 4.1 4.6 5.1 0.022 0.04 5.7 7.2 2.8 5.7 6.4 7.2 0.032 0.052 ns ns ns ns ns ns ns/pF ns/pF -2 Speed -1 Speed Std. Speed -F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5 V PCI Output Module tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH2 dTHL2
Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low
5 V TTL Output Module Timing3 tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH2 dTHL2 dTHLS
2
Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Low to High Delta High to Low Delta High to Low--low slew
2.4 3.1 7.4 2.1 7.4 2.4 3.6 3.1 0.014 0.023 0.043
2.8 3.5 8.5 2.4 8.4 2.8 4.2 3.5 0.017 0.029 0.046
3.1 4.0 9.7 2.7 9.5 3.1 4.7 4.0 0.017 0.031 0.057
3.7 4.7 11.4 3.2 11.0 3.7 5.6 4.7 0.023 0.037 0.066
5.1 6.6 15.9 4.5 15.4 5.1 7.8 6.6 0.031 0.051 0.089
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
Notes: 1. Delays based on 50 pF loading. 2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI - 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 3. Delays based on 35 pF loading.
2 -5 2
v5.1
SX-A Family FPGAs
Package Pin Assignments
208-Pin PQFP
1
208
208-Pin PQFP
Figure 3-1 * 208-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v5.1
3-1
SX-A Family FPGAs
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function GND TDI, I/O I/O NC I/O NC I/O I/O I/O I/O TMS VCCI I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O NC GND VCCA GND I/O TRST, I/O NC I/O I/O I/O NC GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function I/O I/O I/O NC VCCI VCCA I/O I/O I/O I/O I/O I/O NC I/O NC I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
3 -2
v5.1
SX-A Family FPGAs
208-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function I/O I/O NC I/O NC PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O QCLKA I/O PRB,I/O GND VCCA GND NC I/O HCLK VCCI QCLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function NC I/O NC I/O I/O I/O I/O I/O VCCA VCCI NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O GND VCCA GND NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O
v5.1
3-3
SX-A Family FPGAs
208-Pin PQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function NC I/O NC I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O NC NC GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function NC I/O I/O I/O CLKA CLKB NC GND VCCA GND PRA, I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O VCCI NC NC I/O NC I/O I/O TCK, I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O I/O I/O QCLKD I/O CLKA CLKB NC GND VCCA GND PRA, I/O VCCI I/O I/O QCLKC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O
3 -4
v5.1
SX-A Family FPGAs
100-Pin TQFP
100 1
100-Pin TQFP
Figure 3-2 * 100-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v5.1
3-5
SX-A Family FPGAs
100-TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A54SX08A Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA A54SX16A Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA A54SX32A Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
100-TQFP A54SX08A Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O A54SX16A Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O A54SX32A Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O
3 -6
v5.1
SX-A Family FPGAs
100-TQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A54SX08A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O A54SX16A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O
v5.1
3-7
SX-A Family FPGAs
144-Pin TQFP
144 1
144-Pin TQFP
Figure 3-3 * 144-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -8
v5.1
SX-A Family FPGAs
144-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 A54SX08A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O NC VCCA I/O TRST, I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND I/O A54SX16A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O NC VCCA I/O TRST, I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND I/O A54SX32A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O NC VCCA I/O TRST, I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND I/O Pin Number 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
144-Pin TQFP A54SX08A Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O GND I/O A54SX16A Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O GND I/O A54SX32A Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O GND I/O
v5.1
3-9
SX-A Family FPGAs
144-Pin TQFP Pin Number 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 A54SX08A Function I/O I/O I/O I/O VCCA VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCA NC I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O GND I/O A54SX16A Function I/O I/O I/O I/O VCCA VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCA NC I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O GND I/O A54SX32A Function I/O I/O I/O I/O VCCA VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCA NC I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O GND I/O Pin Number 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
144-Pin TQFP A54SX08A Function I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O A54SX16A Function I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O A54SX32A Function I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O
3 -1 0
v5.1
SX-A Family FPGAs
176-Pin TQFP
1
176
176-Pin TQFP
Figure 3-4 * 176-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v5.1
3-11
SX-A Family FPGAs
176-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A54SX32A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O
176-Pin TQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A54SX32A Function I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA NC I/O HCLK I/O I/O I/O
176-Pin TQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND
176-Pin TQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A54SX32A Function VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O
3 -1 2
v5.1
SX-A Family FPGAs
176-Pin TQFP Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 A54SX32A Function I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O
v5.1
3-13
SX-A Family FPGAs
329-Pin PBGA
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Figure 3-5 * 329-Pin PBGA (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -1 4
v5.1
SX-A Family FPGAs
329-Pin PBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 A54SX32A Function GND GND VCCI NC I/O I/O VCCI NC I/O I/O I/O I/O CLKB I/O I/O I/O I/O I/O I/O I/O NC VCCI GND VCCI I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
329-Pin PBGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 AC2 AC3 AC4 AC5 A54SX32A Function I/O I/O I/O I/O I/O TDO, I/O VCCI I/O VCCI I/O GND I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND VCCI NC I/O I/O
329-Pin PBGA Pin Number AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 A54SX32A Function I/O I/O I/O VCCI I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC VCCI GND VCCI GND I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O CLKA I/O I/O I/O I/O I/O I/O
329-Pin PBGA Pin Number B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 A54SX32A Function I/O I/O GND VCCI NC TDI, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND NC I/O I/O I/O TCK, I/O I/O I/O I/O I/O I/O I/O
v5.1
3-15
SX-A Family FPGAs
329-Pin PBGA Pin Number D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E1 E2 E3 E4 E20 E21 E22 E23 F1 F2 F3 F4 F20 F21 F22 F23 G1 G2 G3 G4 G20 G21 G22 G23 A54SX32A Function VCCA NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
329-Pin PBGA Pin Number H1 H2 H3 H4 H20 H21 H22 H23 J1 J2 J3 J4 J20 J21 J22 J23 K1 K2 K3 K4 K10 K11 K12 K13 K14 K20 K21 K22 K23 L1 L2 L3 L4 L10 L11 L12 L13 A54SX32A Function I/O I/O I/O I/O VCCA I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O NC GND GND GND GND
329-Pin PBGA Pin Number L14 L20 L21 L22 L23 M1 M2 M3 M4 M10 M11 M12 M13 M14 M20 M21 M22 M23 N1 N2 N3 N4 N10 N11 N12 N13 N14 N20 N21 N22 N23 P1 P2 P3 P4 P10 P11 A54SX32A Function GND NC I/O I/O NC I/O I/O I/O VCCA GND GND GND GND GND VCCA I/O I/O VCCI I/O TRST, I/O I/O I/O GND GND GND GND GND NC I/O I/O I/O I/O I/O I/O I/O GND GND
329-Pin PBGA Pin Number P12 P13 P14 P20 P21 P22 P23 R1 R2 R3 R4 R20 R21 R22 R23 T1 T2 T3 T4 T20 T21 T22 T23 U1 U2 U3 U4 U20 U21 U22 U23 V1 V2 V3 V4 V20 V21 A54SX32A Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O VCCA I/O I/O VCCI I/O I/O I/O I/O I/O
3 -1 6
v5.1
SX-A Family FPGAs
329-Pin PBGA Pin Number V22 V23 W1 W2 W3 W4 W20 W21 W22 W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCA NC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O
v5.1
3-17
SX-A Family FPGAs
144-Pin FBGA
1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12
Figure 3-6 * 144-Pin FBGA (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -1 8
v5.1
SX-A Family FPGAs
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A54SX08A Function I/O I/O I/O I/O VCCA GND CLKA I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O CLKB I/O I/O I/O GND I/O I/O I/O TCK, I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O A54SX16A Function I/O I/O I/O I/O VCCA GND CLKA I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O CLKB I/O I/O I/O GND I/O I/O I/O TCK, I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O A54SX32A Function I/O I/O I/O I/O VCCA GND CLKA I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O CLKB I/O I/O I/O GND I/O I/O I/O TCK, I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12
144-Pin FBGA A54SX08A Function I/O VCCI TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI VCCI VCCI VCCA I/O GND I/O I/O I/O NC I/O GND GND GND VCCI I/O GND I/O I/O A54SX16A Function I/O VCCI TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI VCCI VCCI VCCA I/O GND I/O I/O I/O NC I/O GND GND GND VCCI I/O GND I/O I/O A54SX32A Function I/O VCCI TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI VCCI VCCI VCCA I/O GND I/O I/O I/O NC I/O GND GND GND VCCI I/O GND I/O I/O
v5.1
3-19
SX-A Family FPGAs
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A54SX08A Function I/O GND I/O I/O GND GND GND VCCI I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCA VCCA VCCI VCCI VCCA I/O I/O NC I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O VCCA A54SX16A Function I/O GND I/O I/O GND GND GND VCCI I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCA VCCA VCCI VCCI VCCA I/O I/O NC I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O VCCA A54SX32A Function I/O GND I/O I/O GND GND GND VCCI I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCA VCCA VCCI VCCI VCCA I/O I/O NC I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O VCCA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
144-Pin FBGA A54SX08A Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O TDO, I/O I/O A54SX16A Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O TDO, I/O I/O A54SX32A Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O TDO, I/O I/O
3 -2 0
v5.1
SX-A Family FPGAs
256-Pin FBGA
1 A B C D E F G H J K L M N P R T 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 3-7 * 256-Pin FBGA (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v5.1
3-21
SX-A Family FPGAs
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 A54SX16A Function GND TCK, I/O I/O I/O I/O I/O I/O I/O CLKB I/O I/O NC I/O I/O GND GND I/O GND I/O I/O I/O NC I/O VCCA I/O I/O NC I/O I/O I/O GND I/O I/O TDI, I/O GND I/O NC A54SX32A Function GND TCK, I/O I/O I/O I/O I/O I/O I/O CLKB I/O I/O I/O I/O I/O GND GND I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND I/O I/O TDI, I/O GND I/O I/O A54SX72A Function GND TCK, I/O I/O I/O I/O I/O I/O I/O CLKB I/O I/O I/O I/O I/O GND GND I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND I/O I/O TDI, I/O GND I/O I/O Pin Number C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
256-Pin FBGA A54SX16A Function I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A54SX32A Function I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A54SX72A Function I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O QCLKD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKC I/O I/O I/O
3 -2 2
v5.1
SX-A Family FPGAs
256-Pin FBGA Pin Number E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 A54SX16A Function I/O I/O NC I/O I/O I/O I/O I/O I/O TMS I/O I/O VCCI VCCI VCCI VCCI I/O VCCA I/O I/O I/O I/O NC I/O NC I/O I/O VCCI GND GND GND GND VCCI I/O GND NC VCCA A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O VCCI VCCI VCCI VCCI I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND VCCI I/O GND I/O VCCA A54SX72A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O VCCI VCCI VCCI VCCI I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND VCCI I/O GND I/O VCCA Pin Number G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4
256-Pin FBGA A54SX16A Function I/O I/O I/O VCCA TRST, I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O NC NC NC NC I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O NC VCCA A54SX32A Function I/O I/O I/O VCCA TRST, I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA A54SX72A Function I/O I/O I/O VCCA TRST, I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA
v5.1
3-23
SX-A Family FPGAs
256-Pin FBGA Pin Number K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 A54SX16A Function I/O VCCI GND GND GND GND VCCI I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O VCCI VCCI VCCI VCCI I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O A54SX32A Function I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCI VCCI VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O A54SX72A Function I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCI VCCI VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKA PRB, I/O I/O Pin Number M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
256-Pin FBGA A54SX16A Function I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O NC I/O I/O I/O I/O NC I/O I/O VCCA I/O A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O A54SX72A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O
3 -2 4
v5.1
SX-A Family FPGAs
256-Pin FBGA Pin Number P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 A54SX16A Function I/O I/O I/O GND I/O NC I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O GND GND GND I/O I/O NC I/O I/O I/O I/O VCCA I/O I/O NC I/O I/O TDO, I/O GND A54SX32A Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O TDO, I/O GND A54SX72A Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HCLK QCLKB I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O TDO, I/O GND
v5.1
3-25
SX-A Family FPGAs
484-Pin FBGA
1 2 3 4 5 6 7 8 9 10 11121314 15161718 19 20212223 242526 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Figure 3-8 * 484-Pin FBGA (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -2 6
v5.1
SX-A Family FPGAs
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 Note: A54SX32A Function NC* NC* NC* NC* NC* I/O I/O I/O I/O I/O NC* NC* I/O NC* NC* NC* I/O I/O I/O I/O NC* NC* NC* NC* NC* NC* NC* NC* VCCA I/O I/O I/O I/O I/O NC* A54SX72A Function NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O VCCA I/O I/O I/O I/O I/O I/O Pin Number AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8
484-Pin FBGA A54SX32A Function NC* NC* VCCI I/O I/O NC* I/O I/O I/O I/O I/O I/O PRB, I/O VCCA I/O I/O I/O I/O I/O I/O TDO, I/O GND NC* I/O I/O NC* NC* I/O I/O I/O NC* VCCI I/O VCCI I/O A54SX72A Function I/O NC VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA I/O I/O I/O I/O I/O I/O TDO, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O VCCI I/O Pin Number AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17
484-Pin FBGA A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O NC* I/O NC* NC* I/O I/O GND I/O I/O I/O I/O I/O VCCI I/O I/O I/O VCCI I/O I/O I/O VCCI A54SX72A Function I/O I/O I/O QCLKA I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCI I/O I/O I/O VCCI I/O I/O I/O VCCI
*These pins must be left floating on the A54SX32A device.
v5.1
3 -27
SX-A Family FPGAs
484-Pin FBGA Pin Number AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 Note: A54SX32A Function I/O I/O I/O I/O I/O VCCI NC* NC* NC* NC* I/O NC* NC* NC* NC* I/O I/O I/O I/O NC* I/O I/O I/O NC* NC* I/O I/O I/O I/O NC* NC* NC* NC* NC* NC* A54SX72A Function I/O I/O I/O I/O I/O VCCI I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC Pin Number AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 B9
484-Pin FBGA A54SX32A Function NC* NC* NC NC* NC* NC* I/O I/O I/O I/O NC* NC* HCLK I/O NC* NC* I/O I/O I/O NC* NC* NC* NC* NC* NC* NC* NC* NC* NC* NC* NC* I/O I/O I/O I/O A54SX72A Function NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC HCLK QCLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O I/O I/O Pin Number B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
484-Pin FBGA A54SX32A Function I/O NC* NC* VCCI CLKA NC* NC* I/O VCCI I/O I/O NC* NC* NC* NC* I/O NC* NC* NC* NC* NC* I/O VCCI I/O I/O VCCI I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O A54SX72A Function I/O I/O I/O VCCI CLKA I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O VCCI I/O I/O VCCI I/O I/O I/O PRA, I/O I/O QCLKD I/O I/O I/O
*These pins must be left floating on the A54SX32A device.
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v5.1
SX-A Family FPGAs
484-Pin FBGA Pin Number C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 Note: A54SX32A Function I/O VCCI I/O I/O I/O I/O NC* NC* NC* TMS I/O VCCI NC* TCK, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O NC* NC* NC* A54SX72A Function I/O VCCI I/O I/O I/O I/O I/O I/O I/O TMS I/O VCCI I/O TCK, I/O I/O I/O I/O I/O I/O QCLKC I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O Pin Number E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26
484-Pin FBGA A54SX32A Function NC* I/O I/O GND TDI, IO I/O I/O I/O I/O I/O I/O VCCA CLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCI NC* NC* I/O I/O I/O I/O I/O I/O NC* A54SX72A Function I/O I/O I/O GND TDI, IO I/O I/O I/O I/O I/O I/O VCCA CLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5
484-Pin FBGA A54SX32A Function NC* NC* NC* I/O I/O I/O VCCA I/O NC* NC* NC* NC* I/O I/O I/O I/O I/O I/O NC* NC* NC* NC* I/O I/O I/O I/O I/O I/O VCCI NC* I/O VCCI I/O I/O VCCA A54SX72A Function I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O VCCI I/O I/O VCCA
*These pins must be left floating on the A54SX32A device.
v5.1
3 -29
SX-A Family FPGAs
484-Pin FBGA Pin Number K10 K11 K12 K13 K14 K15 K16 K17 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L10 L11 L12 L13 L14 L15 L16 L17 L22 L23 L24 L25 L26 M1 M2 M3 M4 Note: A54SX32A Function GND GND GND GND GND GND GND GND I/O I/O NC* NC* NC* NC* NC* I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O NC* I/O I/O I/O A54SX72A Function GND GND GND GND GND GND GND GND I/O I/O NC I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O NC I/O I/O I/O Pin Number M5 M10 M11 M12 M13 M14 M15 M16 M17 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N10 N11 N12 N13 N14 N15 N16 N17 N22 N23 N24 N25 N26 P1 P2 P3
484-Pin FBGA A54SX32A Function I/O GND GND GND GND GND GND GND GND I/O I/O I/O NC* NC* I/O VCCI I/O I/O I/O GND GND GND GND GND GND GND GND VCCA I/O I/O I/O NC* NC* NC* I/O A54SX72A Function I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O GND GND GND GND GND GND GND GND VCCA I/O I/O I/O NC I/O I/O I/O Pin Number P4 P5 P10 P11 P12 P13 P14 P15 P16 P17 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R10 R11 R12 R13 R14 R15 R16 R17 R22 R23 R24 R25 R26 T1 T2
484-Pin FBGA A54SX32A Function I/O VCCA GND GND GND GND GND GND GND GND I/O I/O VCCI I/O I/O NC* NC* I/O I/O TRST, I/O GND GND GND GND GND GND GND GND I/O I/O I/O NC* NC* NC* NC* A54SX72A Function I/O VCCA GND GND GND GND GND GND GND GND I/O I/O VCCI I/O I/O I/O I/O I/O I/O TRST, I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O
*These pins must be left floating on the A54SX32A device.
3 -3 0
v5.1
SX-A Family FPGAs
484-Pin FBGA Pin Number T3 T4 T5 T10 T11 T12 T13 T14 T15 T16 T17 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U10 U11 U12 U13 U14 U15 U16 U17 U22 U23 U24 U25 U26 V1 Note: A54SX32A Function I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O NC* NC* I/O VCCI I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O VCCI I/O NC* A54SX72A Function I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O VCCI I/O I/O Pin Number V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26
484-Pin FBGA A54SX32A Function NC* I/O I/O I/O VCCA I/O I/O NC* NC* I/O I/O I/O I/O I/O I/O VCCA I/O NC* NC* NC* NC* I/O I/O NC* I/O I/O VCCI I/O I/O A54SX72A Function I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O
*These pins must be left floating on the A54SX32A device.
v5.1
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SX-A Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v5 . 1) v5.0 Revised Table 1 and the timing data to reflect the phase out of the -3 speed grade for the A54SX08A device. The "Thermal Characteristics" section was updated. The "176-Pin TQFP" was updated to add pins 81 to 90. The "484-Pin FBGA" was updated to add pins R4 to Y26 v4.0 The "Temperature Grade Offering" is new. The "Speed Grade and Temperature Grade Matrix" is new. "SX-A Family Architecture" was updated. "Clock Resources" was updated. "User Security" was updated. "Power-Up/Down and Hot Swapping" was updated. "Dedicated Mode" is new Table 1-5 is new. "JTAG Instructions" is new "Design Considerations" was updated. The "Programming" section is new. "Design Environment" was updated. "Pin Description" was updated. Table 2-1 was updated. Table 2-2 was updated. Table 2-3 is new. Table 2-4 is new. Table 2-5 was updated. Table 2-6 was updated. "Power Dissipation" is new. Table 2-11 was updated. Table 2-12 was updated. The was updated. The "Sample Path Calculations" were updated. Table 2-13 was updated. 2-11 3-11 3-26 1-iii 1-iii 1-1 1-5 1-7 1-7 1-9 1-9 1-10 1-12 1-13 1-13 1-14 2-1 2-1 2-1 2-1 2-2 2-2 2-8 2-9 2-11 2-14 2-14 2-17 Page
v5.1
4-1
SX-A Family FPGAs
Previous Version Changes in Current Version (v5 . 1) Table 2-13 was updated. All timing tables were updated. v3.0
Page 2-17 2-18 to 2-52
The "Actel Secure Programming Technology with FuseLockTM Prevents Reverse Engineering and 1-i Design Theft" section was updated. The "Ordering Information" section was updated. The "Temperature Grade Offering" section was updated. The Figure 1-1 * SX-A Family Interconnect Elements was updated. The ""Clock Resources" section"was updated The Table 1-1 * SX-A Clock Resources is new. The "User Security" section is new. The "I/O Modules" section was updated. The Table 1-2 * I/O Features was updated. The Table 1-3 * I/O Characteristics for All I/O Configurations is new. The Table 1-4 * Power-Up Time at which I/Os Become Active is new The Figure 1-12 * Device Selection Wizard is new. The "Boundary-Scan Pin Configurations and Functions" section is new. The Table 1-9 * Device Configuration Options for Probe Capability (TRST Pin Reserved) is new. The "SX-A Probe Circuit Control Pins" section was updated. The "Design Considerations" section was updated. The Figure 1-13 * Probe Setup was updated. The Design Environment was updated. The Figure 1-13 * Design Flow is new. The "Absolute Maximum Ratings*" section was updated. The "Recommended Operating Conditions" section was updated. The "Electrical Specifications" section was updated. The "2.5V LVCMOS2 Electrical Specifications" section was updated. The "SX-A Timing Model" and "Sample Path Calculations" equations were updated. The "Pin Description" section was updated. 1-ii 1-iii 1-1 1-5 1-5 1-7 1-7 1-8 1-8 1-8 1-9 1-9 1-11 1-12 1-12 1-12 1-13 1-11 1-12 1-12 1-12 1-13 1-23 1-14 1-13 1-8
v2.0.1
The "Design Environment" section has been updated. The "I/O Modules" section, and Table 1-2 * I/O Features have been updated.
The "SX-A Timing Model" section and the "Timing Characteristics" section have new timing 1-23 numbers.
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SX-A Family FPGAs
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR)
The products described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR) or the Export Administration Regulations (EAR). They may require an approved export license prior to their export. An export can include a release or disclosure to a foreign national inside or outside the United States.
v5.1
4-3
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
www.actel.com
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5172147-8/02.05

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